Datasheet

ADT7470 Data Sheet
Rev. E | Page 4 of 40
SERIAL BUS TIMING SPECIFICATIONS
Table 2.
Parameter
1, 2, 3, 4, 5
Min Typ Max Unit Test Conditions/Comments
SERIAL BUS TIMING
Clock Frequency, f
SCLK
400 kHz See Figure 2
Glitch Immunity, t
SW
50 ns See Figure 2
Bus Free Time, t
BUF
1.3 μs See Figure 2
Start Setup Time, t
SU;STA
600 ns See Figure 2
Start Hold Time, t
HD;STA
600 ns See Figure 2
SCL Low Time, t
LOW
1.3 μs See Figure 2
SCL High Time, t
HIGH
0.6 μs See Figure 2
SCL, SDA Rise Time, t
r
300 ns See Figure 2
SCL, SDA Fall Time, t
f
300 ns See Figure 2
Data Setup Time, t
SU;DAT
100 ns See Figure 2
Detect Clock Low Timeout, t
TIMEOUT
25 28 31 ms
Can be optionally disabled,
via Configuration Register 1
(see Table 6)
1
VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD.
2
All voltages are measured with respect to GND, unless otherwise specified.
3
Typical values are at %A = 25°C and represent the most likely parametric norm.
4
Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V.
5
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
04684-0-002
SCL
SDA
PS
t
BUF
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;DAT
t
HD;STA
t
SU;STA
t
SU;STO
t
LOW
t
R
t
F
SP
Figure 2. Serial Bus Timing Diagram