Datasheet

Data Sheet ADT7470
Rev. E | Page 17 of 40
STATUS REGISTERS
The results of limit comparisons are stored in Status Register 1
and Status Register 2. The status register bit for each channel
reflects the status of the last measurement and limit comparison
on that channel. If a measurement is within limits, the corre-
sponding status register bit is cleared to 0. If the measurement
is out of limit, the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled
by reading the status registers over the serial bus. When Bit 7
(OOL) of Status Register 1 (Register 0x41) is a 1, an out-of-limit
event has been flagged in Status Register 2. This means that
Status Register 2 must be read only when the OOL bit is set.
Reading the status registers clears the appropriate status bit as
long as the error condition that caused the interrupt has cleared.
Status register bits are sticky. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it has gone away (until read). The only way to
clear the status bit is to read the status register when the event has
gone away.
Interrupt status mask registers (Register 0x72 and Register 0x73)
allow individual interrupt sources to be masked from causing an
SMBALERT
. However, if one of these masked interrupt sources
goes out of limit, its associated status bit is still set in the interrupt
status registers. This allows the device to be periodically polled to
determine if an error condition has subsided, without unnecessarily
tying up precious system resources handling interrupt service
routines. The issue is that the device could potentially interrupt the
system every monitoring cycle (< 1 sec) as long as a measurement
parameter remains out of limit. Masking eliminates unwanted
system interrupts.
The OOL bit (Register 0x41 Bit[7]), and the NORM bit
(Register 0x42 Bit[3]) do not activate
SMBALERT
.
Table 12. Interrupt Status Register 1 (Register 0x41)
Bit No. Mnemonic Description
7 OOL A 1 denotes that a bit in Status Register 2 is set and Status Register 2 should now be read.
6 R7T A 1 indicates that TMP05 Temperature 7 high or low limit has been exceeded.
5 R6T A 1 indicates that TMP05 Temperature 6 high or low limit has been exceeded.
4 R5T A 1 indicates that TMP05 Temperature 5 high or low limit has been exceeded.
3 R4T A 1 indicates that TMP05 Temperature 4 high or low limit has been exceeded.
2 R3T A 1 indicates that TMP05 Temperature 3 high or low limit has been exceeded.
1 R2T A 1 indicates that TMP05 Temperature 2 high or low limit has been exceeded.
0 R1T A 1 indicates that TMP05 Temperature 1 high or low limit has been exceeded.
Table 13. Interrupt Status Register 2 (Register 0x42)
Bit No. Mnemonic Description
7 Fan 4 A 1 indicates that Fan 4 has dropped below minimum speed or is above maximum speed.
6 Fan 3 A 1 indicates that Fan 3 has dropped below minimum speed or is above maximum speed.
5 Fan 2 A 1 indicates that Fan 2 has dropped below minimum speed or is above maximum speed.
4 Fan 1 A 1 indicates that Fan 1 has dropped below minimum speed or is above maximum speed.
3 NORM A 1 indicates that the temperatures are below T
MIN
and that the fans are supposed to be off.
2 R10T A 1 indicates that TMP05 Temperature 10 high or low limit has been exceeded.
1 R9T A 1 indicates that TMP05 Temperature 9 high or low limit has been exceeded.
0 R8T A 1 indicates that TMP05 Temperature 8 high or low limit has been exceeded.