Datasheet
ADT7470 Data Sheet
Rev. E | Page 10 of 40
during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation, because the type of operation is
determined at the beginning and subsequently cannot be
changed without starting a new operation.
In the ADT7470, write operations contain either one or two
bytes, and read operations contain one byte and perform the
following functions.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so that the
correct data register is addressed. Then data can be written into
that register or read from it. The first byte of a write operation
always contains an address that is stored in the address pointer
register. If data is to be written to the device, the write operation
contains a second data byte that is written to the register selected
by the address pointer register.
This is illustrated in Figure 7. The device address is sent over the
bus followed by R/
W
set to 0. This is followed by two data bytes.
04684-0-007
1
001 1 1 A1 A0 R/W
991
1
D7 D6 D5 D4 D3 D2 D1 D0
9
D7 D6 D5 D4 D3 D2 D1 D0
SCL
SD
A
SCL (CONTINUED)
SDA (CONTINUED)
START BY
MASTER
ACK. BY
ADT7470
ACK. BY
ADT7470
ACK. BY
ADT7470
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA
BYTE
Figure 7. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register
SCL
SD
A
1
01 01 1A1A0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
ACK. BY
ADT7470
ACK. BY
ADT7470
R/W D7 D6 D5 D4 D3 D2 D1 D0
991
04684-0-008
Figure 8. Writing to the Address Pointer Register Only
04684-0-009
SCL
SD
A
1
01 01 1A1A0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
DATA BYTE FROM
ADT7470
STOP BY
MASTER
ACK. BY
ADT7470
NO ACK.
BY MASTER
R/W D7 D6 D5 D4 D3 D2 D1 D0
991
Figure 9. Reading Data from a Previously Selected Register