Datasheet

Data Sheet ADT7420
Rev. 0 | Page 5 of 24
I
2
C TIMING SPECIFICATIONS
T
A
= −40°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL INTERFACE
1
See Figure 2
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 μs
SCL Low Pulse Width, t
LOW
1.3 μs
SCL, SDA Rise Time, t
R
0.3 μs
SCL, SDA Fall Time, t
F
0.3 μs
Hold Time (Start Condition), t
HD:STA
0.6 μs After this period, the first clock is generated
Setup Time (Start Condition), t
SU:STA
0.6 μs Relevant for repeated start condition
Data Setup Time, t
SU:DAT
0.02 μs
Setup Time (Stop Condition), t
SU:STO
0.6 μs
Data Hold Time, t
HD:DAT
(Master) 0.03 μs
Bus-Free Time (Between Stop and Start Condition), t
BUF
1.3 μs
Capacitive Load for Each Bus Line, C
B
400 pF
1
Sample tested during initial release to ensure compliance.
Timing Diagram
P
S
t
LOW
t
R
t
F
t
HD:ST A
t
HD:DA T
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
HIGH
SCL
PS
SDA
t
BUF
09013-002
Figure 2. Serial Interface Timing Diagram