Datasheet

ADT7420 Data Sheet
Rev. 0 | Page 24 of 24
OUTLINE DIMENSIONS
2.70
2.60 SQ
2.50
COMPLIANT
TO JEDEC STANDARDS MO-220-WGGC.
012909-B
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
P
I
N
1
I
N
D
I
C
A
T
O
R
4.10
4.00 SQ
3.90
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDI
C
ATOR
0.35
0.30
0.25
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 21. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Operating Temperature Range Package Description Package Option
ADT7420UCPZ-R2 −40°C to +150°C 16-lead LFCSP_WQ CP-16-17
ADT7420UCPZ-RL7 −40°C to +150°C 16-lead LFCSP_WQ CP-16-17
EVAL-ADT7X20EBZ Evaluation Board
1
Z = RoHS Compliant Part.
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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D09013-0-12/12(0)