Datasheet

ADT7411
Rev. B | Page 5 of 36
Parameter
1
Min Typ Max Unit Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7 5.5 V
V
DD
Settling Time 50 ms V
DD
settles to within 10% of its final voltage level.
I
DD
(Normal Mode)
8
3 mA V
DD
= 3.3 V, V
IH
= V
DD
and V
IL
= GND.
2.2 3 mA V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
I
DD
(Power-Down Mode) 10 μA V
DD
= 3.3 V, V
IH
= V
DD
and V
IL
= GND.
10 μA V
DD
= 5 V, V
IH
= V
DD
and V
IL
= GND.
Power Dissipation 10 mW V
DD
= 3.3 V. Using normal mode.
33 μW V
DD
= 3.3 V. Using shutdown mode.
1
See the Terminology section.
2
Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3
Guaranteed by design and characterization, not production tested.
4
The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I
2
C specification. Switching off the input filters improves the transfer
rate but has a negative effect on the EMC behavior of the part.
5
Guaranteed by design. Not tested in production.
6
The interface is also capable of handling the I
2
C standard mode rise time specification of 1000 ns.
7
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
8
I
DD
specification is valid for full-scale analog input voltages. Interface inactive. ADC active. Load currents excluded.
SCL
t
4
t
2
t
1
t
3
t
5
t
6
SDA
DATA IN
SDA
DATA OUT
02882-002
t
7
Figure 2. I
2
C Bus Timing Diagram
t
1
t
2
t
3
t
5
t
6
t
4
t
7
t
8
D7
CS
SCLK
DIN
DOUT
D6D5D4D3D2D1D0XX XXXXX X
X X X X X X X X D7D6 D5 D4D3D2D1 D0
02882-003
Figure 3. SPI Bus Timing Diagram
200µA I
OH
1.6V
TO
OUTPUT
PIN
C
L
50pF
200µA I
OL
02882-004
Figure 4. Load Circuit for Access Time and Bus Relinquish Time