Datasheet

ADT7411
Rev. B | Page 4 of 36
Parameter
1
Min Typ Max Unit Conditions/Comments
ROUND ROBIN UPDATE RATE
2
Time to complete one measurement cycle
thr
ough all channels.
Slow ADC @ 25°C
Averaging On 125.4 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging Off 17.1 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging On 140.36 ms D+ and D– are selected on Pin 7 and Pin 8.
Averaging Off 12.11 ms D+ and D− are selected on Pin 7 and Pin 8.
Fast ADC @ 25°C
Averaging On 9.26 ms AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging Off 578.96 μs AIN1 and AIN2 are selected on Pin 7 and Pin 8.
Averaging On 24.62 ms D+ and D− are selected on Pin 7 and Pin 8.
Averaging Off 3.25 ms D+ and D− are selected on Pin 7 and Pin 8.
ON-CHIP REFERENCE
3
Reference Voltage 2.2662 2.28 2.2938 V
Temperature Coefficient 80 ppm/°C
DIGITAL INPUTS
1, 3
Input Current ±1 μA V
IN
= 0 V to V
DD
.
V
IL
, Input Low Voltage 0.8 V
V
IH
, Input High Voltage 1.89 V
Pin Capacitance 3 10 pF All digital inputs.
SCL, SDA Glitch Rejection 50 ns
Input filtering suppresses n
oise spikes of less
than 50 ns.
DIGITAL OUTPUTS
Output High Voltage, V
OH
2.4 V I
SOURCE
= I
SINK
= 200 μA.
Output Low Voltage, V
OL
0.4 V I
OL
= 3 mA.
Output High Current, I
OH
1 mA V
OH
= 5 V.
Output Capacitance, C
OUT
50 pF
INT/INT Output Saturation Voltage
0.8 V I
OUT
= 4 mA.
I
2
C TIMING CHARACTERISTICS
4, 5
Serial Clock Period, t
1
2.5 μs Fast-mode I
2
C. See Figure 2.
Data In Setup Time to SCL High, t
2
50 ns
Data Out Stable after SCL Low, t
3
0 ns See Figure 2.
SDA Low Setup Time to SCL Low
(Start Condition), t
4
50 ns See Figure 2.
SDA High Hold Time after SCL High
(Stop Condition), t
5
50 ns See Figure 2.
SDA and SCL Fall Time, t
6
300 ns See Figure 2.
SDA and SCL Rise Time, t
7
300
6
ns See Figure 2.
SPI TIMING CHARACTERISTICS
1, 3, 7
CS to SCLK Setup Time, t
1
0 ns See Figure 3.
SCLK High Pulse Width, t
2
50 ns See Figure 3.
SCLK Low Pulse Width, t
3
50 ns See Figure 3.
Data Access Time after SCLK Falling Edge, t
4
7
35 ns See Figure 3.
Data Setup Time Prior to SCLK Rising Edge, t
5
20 ns See Figure 3.
Data Hold Time after SCLK Rising Edge, t
6
0 ns See Figure 3.
CS to SCLK Hold Time, t
7
0 ns See Figure 3.
CS to DOUT High Impedance, t
8
40 ns See Figure 3.