Datasheet

ADT7411
Rev. B | Page 29 of 36
SPI Lock Status Register (Read-Only) [Address = 7Fh]
Bit D0 (LSB) of this read-only register indicates whether the SPI
interface is locked or not. Writing to this register causes the
device to malfunction.
Default value is 00h.
0 = I
2
C interface.
1 = SPI interface selected and locked.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part: I
2
C
and SPI. The device powers up with the serial interface in I
2
C
mode, but it is not locked into this mode. To stay in I
2
C mode, it
is recommended that the user tie the
CS
line to either V
CC
or
GND. It is not possible to lock the I
2
C mode, but it is possible to
select and lock the SPI mode.
To select and lock the interface into the SPI mode, a number of
p
ulses must be sent down the
CS
(Pin 4) line. The following
section describes how this is done.
Once the SPI communication protocol is locked in, it cannot be
unlo
cked while the device is still powered up. Bit D0 of the SPI
Lock Status register (Address 7Fh) is set to 1 when a successful
SPI interface lock is accomplished. To reset the serial interface,
the user must power down the part and power up again. A
software reset does not reset the serial interface.
Serial Interface Selection
The
CS
line controls the selection between I
2
C and SPI.
Figure 33 shows the selection process necessary to lock the SPI
in
terface mode.
To communicate to the ADT7411 using the SPI protocol, send
t
hree pulses down the
CS
line, as shown in Figure 33. On the
third rising edge (marked as C in Figure 33), the part selects
a
nd locks the SPI interface. Communication to the device is
now limited to the SPI protocol.
As per most SPI standards, the
CS
line must be low during
every SPI communication to the ADT7411, and high at all other
times. Typical examples of how to connect the dual interface as
I
2
C or SPI are shown in Figure 31 and Figure 32.
ADT7411
CS
SDA
SCL
ADD
V
DD
V
DD
I
2
C ADDRESS = 1001 000
10kΩ10kΩ
02882-030
Figure 31. Typical I
2
C Interface Connection
ADT7411
SCLK
DOUT
CS
V
DD
LOCK AND
SELECT SPI
SPI FRAMING
EDGE
820Ω 820Ω 820Ω
DIN
02882-031
Figure 32. Typical SPI Interface Connection
The following sections describe in detail how to use the I
2
C and
SPI protocols associated with the ADT7411.
I
2
C Serial Interface
Like all I
2
C compatible devices, the ADT7411 has a 7-bit serial
address. The four MSBs of this address for the ADT7411 are set
to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
Address 1001 010, and setting it high gives the Address 1001
011. The recommended pull-up resistor value is 10 kΩ.
There is an enable/disable bit for the SMBus timeout. When this
i
s enabled, the SMBus times out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-up default is with the SMBus timeout disabled.
The ADT7411 supports SMBus packet error checking (PEC)
a
nd its use is optional. It is triggered by supplying the extra
clocks for the PEC byte. The PEC is calculated using CRC-8.
The frame clock sequence (FCS) conforms to CRC-8 by the
polynomial
C (x) =
x
8
+ x
2
+ x
1
+1
Consult the SMBus specification for more information.
The serial bus protocol operates as follows:
1. The mast
er initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/
W
bit, which
determines the direction of the data transfer, that is,
whether data is written to or read from the slave device.