Datasheet

ADT7411
Rev. B | Page 14 of 36
FUNCTIONAL DESCRIPTION
ANALOG INPUTS
Single-Ended Inputs
The ADT7411 offers eight single-ended analog input channels.
The analog input range is from 0 V to 2.25 V or 0 V to V
DD
. To
maintain the linearity specification, it is recommended that the
maximum V
DD
value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration 3
register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
reference of 2.25 V. Setting the bit to 1 sets up the ADC
reference to be sourced from V
DD
.
The ADC resolution is 10 bits and is mostly suitable for dc
in
put signals or very slowly varying ac signals. Bit C1 and
Bit C2 of the Control Configuration 1 register (Address 18h) are
used to set up Pin 7 and Pin 8 as AIN1 and AIN2.
Figure 20
s
hows the overall view of the 8-channel analog input path.
M
U
L
T
I
P
L
E
X
E
R
10-BIT
ADC
TO ADC
VALUE
REGISTER
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
02882-019
Figure 20. Octal Analog Input Path
Converter Operation
The analog input channels use a successive approximation ADC
based around a capacitor DAC. Figure 21 and Figure 22 show
sim
plified schematics of the ADC. Figure 21 shows the ADC
d
uring acquisition phase. SW2 is closed and SW1 is in Position A.
The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
CONTROL
LOGIC
CAP DAC
ACQUISITION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT
V
REF
REF
V
DD
A
IN
SW1
A
B
SW2
REF/2
02882-021
Figure 21. ADC Acquisition Phase
When the ADC eventually goes into conversion phase (see
Figure 22) SW2 opens and SW1 moves to Position B, causing
th
e comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Figure 24 shows the ADC transfer function for
sin
gle-ended analog inputs.
CONTROL
LOGIC
CAP DAC
CONVERSION
PHASE
SAMPLING
CAPACITOR
COMPARATOR
INT
V
REF
REF
V
DD
A
IN
SW1
A
B
SW2
REF/2
0
2882-022
Figure 22. ADC Conversion Phase
C1
D+
LOW-PASS
FILTER
f
C
= 65kHz
BIAS
DIODE
V
DD
TO ADC
V
OUT+
V
OUT–
REMOTE
SENSING
TRANSISTOR
(2N3906)
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
D–
I N × I I
BIAS
02882-020
Figure 23. Signal Conditioning for External Diode Temperature Sensor