Datasheet

ADT7410 Data Sheet
Rev. A | Page 4 of 24
I
2
C TIMING SPECIFICATIONS
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL INTERFACE
1, 2
See Figure 2
SCL Frequency 0 400 kHz
SCL High Pulse Width, t
HIGH
0.6 μs
SCL Low Pulse Width, t
LOW
1.3 μs
SCL, SDA Rise Time, t
R
0.3 μs
SCL, SDA Fall Time, t
F
0.3 μs
Hold Time (Start Condition), t
HD;STA
0.6 μs After this period, the first clock is generated
Setup Time (Start Condition), t
SU;STA
0.6 μs Relevant for repeated start condition
Data Setup Time, t
SU;DAT
0.25 μs V
DD
≥ 3.0 V
0.35 μs V
DD
< 3.0 V
Setup Time (Stop Condition), t
SU;STO
0.6 μs
Data Hold Time, t
HD;DAT
(Master) 0 μs
Bus-Free Time (Between Stop and Start Condition), t
BUF
1.3 μs
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
Timing Diagram
06560-002
P
S
t
LOW
t
R
t
F
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
t
HIGH
SCL
PS
SDA
t
BUF
Figure 2. Serial Interface Timing Diagram