Datasheet

Data Sheet ADT7410
Rev. A | Page 15 of 24
T
HIGH
SETPOINT REGISTERS
The T
HIGH
setpoint MSB and T
HIGH
setpoint LSB registers store
the overtemperature limit value. An overtemperature event
occurs when the temperature value stored in the temperature
value register exceeds the value stored in this register. The INT
pin is activated if an overtemperature event occurs. The temper-
ature is stored in twos complement format with the MSB being
the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x04 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x05. Only
Register Address 0x04 (T
HIGH
setpoint MSB) needs to be loaded
into the address pointer register as the address pointer auto-
increments to Register Address 0x05 (T
HIGH
setpoint LSB).
The default setting for the T
HIGH
setpoint is 64°C.
T
LOW
SETPOINT REGISTERS
The T
LOW
setpoint MSB and T
LOW
setpoint LSB registers store
the undertemperature limit value. An undertemperature event
occurs when the temperature value stored in the temperature
value register is less than the value stored in this register. The
INT pin is activated if an undertemperature event occurs. The
temperature is stored in twos complement format with the MSB
being the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit
8) are read first from Register Address 0x06 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x07. Only
the Register Address 0x06 (T
LOW
setpoint MSB) needs to be
loaded into the address pointer register as the address pointer
auto-increments to Register Address 0x07 (T
LOW
setpoint LSB).
The default setting for the T
LOW
setpoint is 10°C.
T
CRIT
SETPOINT REGISTERS
The T
CRIT
setpoint MSB and T
CRIT
setpoint LSB registers store
the critical overtemperature limit value. A critical overtempe-
rature event occurs when the temperature value stored in the
temperature value register exceeds the value stored in this
register. The CT pin is activated if a critical overtemperature
event occurs. The temperature is stored in twos complement
format with the MSB being the temperature sign bit.
When reading from this register, the eight MSBs (Bit 15 to Bit 8)
are read first from Register Address 0x08 and then the eight
LSBs (Bit 7 to Bit 0) are read from Register Address 0x09.
Only the Register Address 0x08 (T
CRIT
setpoint MSB) needs to
be loaded into the address pointer register as the address pointer
auto-increments to Register Address 0x09 (T
CRIT
setpoint LSB).
The default setting for the T
CRIT
limit is 147°C.
Table 12. T
HIGH
Setpoint MSB Register (Register Address 0x04)
Bit
Default Value
Type
Name
Description
[15:8] 0x20
R/
W
T
HIGH
MSB MSBs of the overtemperature limit, stored in twos complement format.
Table 13. T
HIGH
Setpoint LSB Register (Register Address 0x05)
Bit Default Value Type Name Description
[7:0] 0x00
R/
W
T
HIGH
LSB LSBs of the overtemperature limit, stored in twos complement format.
Table 14. T
LOW
Setpoint MSB Register (Register Address 0x06)
Bit Default Value Type Name Description
[15:8] 0x05
R/
W
T
LOW
MSB MSBs of the undertemperature limit, stored in twos complement format.
Table 15. T
LOW
Setpoint LSB Register (Register Address 0x07)
Bit Default Value Type Name Description
[7:0] 0x00
R/
W
T
LOW
LSB LSBs of the undertemperature limit, stored in twos complement format.
Table 16. T
CRIT
Setpoint MSB Register (Register Address 0x08)
Bit Default Value Type Name Description
[15:8] 0x49
R/
W
T
CRIT
MSB MSBs of the critical overtemperature limit, stored in twos complement format.
Table 17. T
CRIT
Setpoint LSB Register (Register Address 0x09)
Bit Default Value Type Name Description
[7:0] 0x80
R/
W
T
CRIT
LSB LSBs of the critical overtemperature limit, stored in twos complement format.