Datasheet

ADT7408
Rev. 0 | Page 4 of 24
TIMING CHARACTERISTICS
T
A
= −20°C to +125°C, V
DD
= 3.0 V to 3.6 V, unless otherwise noted.
Table 2.
Parameter
1
Symbol Min Typ Max Unit Comments
SCL Clock Frequency f
SCL
10 100 kHz
Bus Free Time Between a Stop (P) and Start (S) Condition t
BUF
4.7 s
Hold Time After (Repeated) Start Condition t
HD:STA
4.0 s
After this period, the first clock
is generated.
Repeated Start Condition Setup Time t
SU:STA
4.7 s
High Period of the SCL Clock t
HIGH
4.0 50 s
Low Period of the SCL Clock t
LOW
4.7 s
Fall Time of Both SDA and SCL Signals t
F
300 ns
Rise Time of Both SDA and SCL Signals t
R
1000 ns
Data Setup Time t
SU:DAT
250 ns
Data Hold Time t
HD:DAT
300 ns
Setup Time for Stop Condition t
SU:STO
4.0 s
Capacitive Load for Each Bus Line, C
B
400 pF
1
Guaranteed by design and characterization, not production tested.
TIMING DIAGRAM
SCL
SDA
PS P
05716-002
V
IH
S
t
R
t
R
t
F
t
F
t
SU:DAT
t
HIGH
t
HD:DAT
t
BUF
t
LOW
t
SU:STA
t
SU:STO
t
HD:STA
V
IL
V
IH
V
IL
Figure 2. SMBus/I
2
C Timing Diagram