Datasheet
ADT7320 Data Sheet
Rev. 0 | Page 4 of 24
Parameter Min Typ Max Unit Test Conditions/Comments
Shutdown Current Supply current in shutdown mode
At 3.3 V 2.0 15 µA
At 5.5 V 5.2 25 µA
Power Dissipation, Normal Mode 700 µW V
DD
= 3.3 V, normal mode at 25°C
Power Dissipation, 1 SPS Mode
150
µW
Power dissipated for V
DD
= 3.3 V, T
A
= 25°C
1
Accuracy specification includes repeatability.
2
The equivalent 3 σ limits are ±0.15°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits.
3
For higher accuracy at 5 V operation, contact Analog Devices, Inc.
4
Temperature hysteresis does not include repeatability.
5
Based on a floating average of 10 readings.
6
Drift includes solder heat resistance and lifetime test performed as per JEDEC Standard JESD22-A108.
SPI TIMING SPECIFICATIONS
T
A
= −40°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Descriptions
t
1
0 ns min
CS
falling edge to SCLK active edge setup time
t
2
100 ns min SCLK high pulse width
t
3
100 ns min SCLK low pulse width
t
4
30
ns min
Data setup time prior to SCLK rising edge
t
5
25 ns min Data hold time after SCLK rising edge
t
6
5 ns min Data access time after SCLK falling edge
60 ns max V
DD
= 4.5 V to 5.5 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
7
3
10 ns min Bus relinquish time after
CS
inactive edge
80 ns max Bus relinquish time after
CS
inactive edge
t
8
0 ns min SCLK inactive edge to
CS
rising edge hold time
t
9
0 ns min
CS
falling edge to DOUT active time
60 ns max V
DD
= 4.5 V to 5.5 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
10
10
ns min
SCLK inactive edge to DOUT low
1
Sample tested during initial release to ensure compliance.
2
See Figure 2.
3
This means that the times quoted in the timing characteristics in Table 2 are the true bus relinquish times of the part and, as such, are independent of external bus
loading capacitances.
CS
SCLK
DIN
DOUT
t
1
1
8
76
MSB LSB
2 3
MSB
LSB
9 10 23 24
t
2
t
4
t
5
t
3
t
6
t
7
t
8
t
9
t
10
09012-002
Figure 2. Detailed SPI Timing Diagram