Datasheet

ADT7316/ADT7317/ADT7318
Rev. B | Page 5 of 44
Parameter
1
Min Typ Max Unit Conditions/Comments
DIGITAL OUTPUT
Output High Voltage, V
OH
2.4 V I
SOURCE
= I
SINK
= 200 μA.
Output Low Voltage, V
OL
0.4 V I
OL
= 3 mA.
Output High Current, I
OH
1 mA V
OH
= 5 V.
Output Capacitance, C
OUT
50 pF
INT/
INT
Output Saturation Voltage
0.8 V I
OUT
= 4 mA.
I
2
C TIMING CHARACTERISTICS
7, 8
Serial Clock Period, t
1
2.5 μs
Fast-mode I
2
C. See Figure 4.
Data In Setup Time to SCL High, t
2
50 ns
Data Out Stable After SCL Low, t
3
0 ns
See
Figure 4.
SDA Low Setup Time to SCL Low
(Start Condition), t
4
50 ns
See
Figure 4.
SDA High Hold Time After SCL High
(Stop Condition), t
5
50 ns
See
Figure 4.
SDA and SCL Fall Time, t
6
300 ns
See
Figure 4.
SDA and SCL Rise Time, t
6
300
9
ns
See
Figure 4.
SPI TIMING CHARACTERISTICS
10, 11
CS
to SCLK Setup Time, t
1
0 ns
See
Figure 7.
SCLK High Pulse Width, t
2
50 ns
See
Figure 7.
SCLK Low Pulse Width, t
3
50 ns
See
Figure 7.
Data Access Time After SCLK Falling
Edge, t
4
12
35 ns
See
Figure 7.
Data Setup Time Prior to SCLK
Rising Edge, t
5
20 ns
See
Figure 7.
Data Hold Time after SCLK Rising
Edge, t
6
0 ns
See
Figure 7.
CS
to SCLK Hold Time, t
7
0 ns
See
Figure 7.
CS
to DOUT High Impedance, t
8
40 ns
See
Figure 7.
POWER REQUIREMENTS
V
DD
2.7 5.5 V
V
DD
Settling Time 50 ms V
DD
settles to within 10% of its final voltage level.
I
DD
(Normal Mode)
13
3 mA V
DD
= 3.3 V, V
IH
= V
DD
, and V
IL
= GND.
2.2 3 mA V
DD
= 5 V, V
IH
= V
DD
, and V
IL
= GND.
I
DD
(Power-Down Mode) 10 μA V
DD
= 3.3 V, V
IH
= V
DD
, and V
IL
= GND.
10 μA V
DD
= 5 V, V
IH
= V
DD
, and V
IL
= GND.
Power Dissipation 10 mW V
DD
= 3.3 V, using normal mode.
33 μW V
DD
= 3.3 V, using shutdown mode.
1
See the Terminology section.
2
DC specifications tested with the outputs unloaded.
3
Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).
4
A round robin is the continuous sequential measurement of the following three channels: V
DD
, internal temperature, and external temperature.
5
Guaranteed by design and characterization, but not production tested.
6
For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
, offset plus
gain error must be positive.
7
The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I
2
C specification. Switching off the input filters improves the transfer rate,
but has a negative effect on the EMC behavior of the part.
8
Guaranteed by design. Not tested in production.
9
The interface is also capable of handling the I
2
C standard mode rise time specification of 1000 ns.
10
Guaranteed by design and characterization, but not production tested.
11
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
12
Measured with the load circuit of Figure 5.
13
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.