Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsADT7316ARQZ-REEL7

ADT7316/ADT7317/ADT7318

Rev. B | Page 38 of 44

Write Operation

Figure 54 and Figure 55 show the timing diagrams for a write

operation to the ADT7316/ADT7317/ADT7318. Data is clocked

into the registers on the rising edge of SCLK. When the

line

is high, the DIN and DOUT lines are in three-state mode. Only

when the

goes from a high to a low does the part accept any

data on the DIN line. In SPI mode, the address pointer register

is capable of an auto-increment to the next register in the register

map without having to load the address pointer register each

time. In

Figure 54, the register address section provides the first

egister address that is written to. Subsequent data bytes are

written into sequential writable registers. Therefore, after each

data byte has been written into a register, the address pointer

The address pointer register auto-increments from Address

0x00 to Address 0x3F and loops back to start all over again at

Address 0x00 when it reaches Address 0x3F.

1SDA

START BY

MASTER

STOP BY

MASTER

NO ACKNOWLEDGE BY

MASTER

ACKNOWLEDGE BY

ADT7316/ADT7317/ADT7318

SCL

0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

SINGLE DATA BYTE FROM ADT7316/ADT7317/ADT7318

191

02661-053

Figure 53. I

C — Reading a Single Byte of Data From a Selected Register

START

181

SCLK

DIN

STOP

CS (CONTINUED)

SCLK (CONTINUED)

DATA BYTE

DIN (CONTINUED)

02661-054

Figure 54. SPI—Writing to the Address Pointer

DIN

SCLK

START

WRITE COMMAND

181

STOP

02661-055

Figure 55. SPI—Writing to the Address P

ointer Register to Select a Register for a Subsequent Read Operation