Datasheet

ADT7310 Data Sheet
Rev. A | Page 4 of 24
SPI TIMING SPECIFICATIONS
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
(B Version) Unit Conditions/Comments
t
1
0 ns min
CS
falling edge to SCLK active edge setup time
3
t
2
100 ns min SCLK high pulse width
t
3
100 ns min SCLK low pulse width
t
4
30 ns min Data valid to SCLK edge setup time
t
5
25 ns min Data valid to SCLK edge hold time
t
6
0 ns min SCLK active edge to data valid delay
3
60 ns max V
DD
= 4.5 V to 5.5 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
7
4
10 ns min
Bus relinquish time after CS
inactive edge
80 ns max
t
8
0 ns min
CS
rising edge to SCLK edge hold time
t
9
0 ns min
CS
falling edge to DOUT active time
60 ns max V
DD
= 4.5 V to 5.5 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
10
10 ns min SCLK inactive edge to DOUT high
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
SCLK active edge is falling edge of SCLK.
4
This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
07789-002
CS
SCLK
DIN
DOUT
t
1
1
8
7
MSB LSB
23
MSB
LSB
12
7
8
t
2
t
4
t
5
t
3
t
6
t
7
t
8
t
9
t
10
Figure 2. Detailed SPI Timing Diagram
1.6V
10pF
TO
OUTPUT
PIN
I
SINK
(1.6mA WITH V
DD
= 5V,
100µA WITH V
DD
= 3V)
I
SOURCE
(200µA WITH V
DD
=5V,
100µA WITH V
DD
= 3V)
07789-004
Figure 3. Load Circuit for Timing Characterization