Datasheet

ADT7301
Rev. 0 | Page 4 of 16
TIMING CHARACTERISTICS
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
)
and timed from a voltage level of 1.6 V. T
A
= T
MIN
to T
MAX
, V
DD
= 2.7 V to 5.25 V, unless otherwise noted.
Table 2.
Parameter
1
Limit Unit Comments
t
1
5 ns min
CS
to SCLK set-up time
t
2
25 ns min SCLK high pulse width
t
3
25 ns min SCLK low pulse width
t
4
2
35 ns max Data access time after SCLK falling edge
t
5
20 ns min Data set-up time prior to SCLK rising edge
t
6
5 ns min Data hold time after SCLK rising edge
t
7
5 ns min
CS
to SCLK hold time
t
8
2
40 ns max
CS
to DOUT high Impedance
1
See Figure 14 for the SPI timing diagram.
2
Measured with the load circuit of Figure 2.
1.6V
200μA
200μAI
OH
I
OL
02884-0-002
TO
OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time