Datasheet

Rev. D | Page 36 of 48 | May 2012
ADSP-TS203S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, C
L
, and the drive current, I
D
.
This ramp time can be approximated by the following equation:
The output enable time t
ENA
is the difference between
t
MEASURED_ENA
and t
RAMP
as shown in Figure 33. The time
t
MEASURED_ENA
is the interval from when the reference signal
switches to when the output voltage ramps ΔV from the mea-
sured three-stated output level. t
RAMP
is calculated with test load
C
L
, drive current I
D
, and with ΔV equal to 0.4 V.
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see Figure 34). The delay and hold specifica-
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF. Figure 35
through Figure 42 show how output rise time varies with capac-
itance. Figure 43 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 35.) The graphs of Figure 35 through Figure 43 may not be
linear outside the ranges shown.
Figure 33. Output Enable/Disable
Figure 34. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
– DV
V
OL (MEASURED)
+ DV
t
MEASURED_DIS
V
OH (MEASURED)
V
OL (MEASURED)
1.65V
0.85V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.25V.
OUTPUT STOPS
DRIVING
t
DECAY
t
ENA
t
MEASURED_ENA
t
RAMP
t
RAMP
C
L
VΔ()I
D
⁄=
1.25V
TO
OUTPUT
PIN
30pF
50V
Figure 35. Typical Output Rise and Fall Time (10% to 90%, V
DD_IO
=2.5V)
vs. Load Capacitance at Strength 0
Figure 36. Typical Output Rise and Fall Time (10% to 90%, V
DD_IO
=2.5V)
vs. Load Capacitance at Strength 1
0
10 20 30 40 50 60 70 80 90 100
0
5
10
15
20
25
RISE TIME
Y = 0.259x + 3.0842
STRENGTH 0
(V
DD_IO
=2.5V)
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
LOAD CAPACITANCE (pF)
FALL TIME
Y = 0.251x + 4.2245
0 102030 40506070 8090100
0
5
10
15
20
25
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
LOAD CAPACITANCE (pF)
STRENGTH 1
(V
DD_IO
=2.5V)
RISE TIME
Y = 0.1501
x +0.05
FALL TIME
Y = 0.1527x + 0.7485