Datasheet

Rev. D | Page 20 of 48 | May 2012
ADSP-TS203S
SPECIFICATIONS
Note that component specifications are subject to change with
out notice. For information on link port electrical characteris-
tics, see Link Port Low Voltage, Differential-Signal (LVDS)
Electrical Characteristics, and Timing on Page 29.
OPERATING CONDITIONS
Parameter Description Test Conditions Grade
1
1
Specifications vary for different grades (for example, SABP–060, SABP–050, SWBP–050). For more information on part grades, see Ordering Guide on Page 47.
Min Typ Max Unit
V
DD
Internal Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V
V
DD_A
Analog Supply Voltage @ CCLK = 500 MHz 050 1.00 1.05 1.10 V
V
DD_IO
I/O Supply Voltage (all) 2.38 2.50 2.63 V
V
DD_DRAM
Internal DRAM Supply Voltage @ CCLK = 500 MHz 050 1.425 1.500 1.575 V
T
CASE
Case Operating Temperature A –40 +85 °C
T
CASE
Case Operating Temperature B 0 +85 °C
V
IH1
High Level Input Voltage
2, 3
2
V
IH1
specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0, RAS,
CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.
3
Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is
equivalent to 100% duty cycle.
@ V
DD
, V
DD_IO
= Max (all) 1.7 3.63 V
V
IH2
High Level Input Voltage
3, 4
4
V
IH2
specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.
@ V
DD
, V
DD_IO
= Max (all) 1.9 3.63 V
V
IL
Low Level Input Voltage
3, 5
5
Applies to input and bidirectional pins.
@ V
DD
, V
DD_IO
= Min (all) –0.33 +0.8 V
I
DD
V
DD
Supply Current, Typical Activity
6
6
For details on internal and external power calculation issues, including other operating conditions, see EE-170, Estimating Power for the ADSP-TS203S.
@ CCLK = 500 MHz, V
DD
= 1.05 V,
T
CASE
= 25°C 050 2.06 A
I
DD_A
V
DD_A
Supply Current, Typical Activity
@ CCLK = 500 MHz, V
DD
= 1.05 V,
T
CASE
= 25°C 050 20 50 mA
I
DD_IO
V
DD_IO
Supply Current, Typical Activity
6
@ SCLK = 62.5 MHz, V
DD_IO
= 2.5 V,
T
CASE
= 25°C (all) 0.15 A
I
DD_DRAM
V
DD_DRAM
Supply Current,
Typical Activity
6
@ CCLK = 500 MHz, V
DD_DRAM
= 1.5 V,
T
CASE
= 25°C 050 0.25 0.40 A
V
REF
Voltage Reference (all) (V
DD_IO
×0.56)±5% V
SCLK_V
REF
Voltage Reference (all) (V
CLOCK _ DRIVE
× 0.56) ±5% V
Table 18. Maximum Duty Cycle for Input Transient Voltage
V
IN
Max (V)
1
1
The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages
specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding
duty cycle.
V
IN
Min (V)
1
Maximum Duty Cycle
2
2
Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. This is equivalent to the measured duration of a single instance of overshoot or
undershoot as a percentage of the period of occurrence. The practical worst case for period of occurrence for either overshoot or undershoot is 2 × t
SCLK
.
+3.63 –0.33 100%
+3.64 –0.34 90%
+3.70 –0.40 50%
+3.78 –0.48 30%
+3.86 –0.56 17%
+3.93 –0.63 10%