Datasheet

ADSP-TS203S
Rev. D | Page 19 of 48 | May 2012
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a 500 Ω
resistor connected to V
DD_IO
is required. If providing external
pull-downs, do not strap these pins directly to V
SS
; the strap
pins require 500 Ω resistor straps.
All strap pins are sampled on the rising edge of RST_IN
(deas-
sertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN
). Shortly after deas-
sertion of RST_IN
, these pins are reconfigured to their normal
functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN
is active (low) or if RST_IN is deasserted (high).
Table 17 shows the resistors that are enabled during active reset
and during normal operation.
SYS_REG_WE I (pd_0) BUSLOCK SYSCON and SDRCON Write Enable.
0 = one-time writable after reset (default)
1 = always writable
TM1 I (pu) L1BCMPO Test Mode 1. Do not overdrive default value during reset.
TM2 I (pu) TM2 Test Mode 2. Do not overdrive default value during reset.
TM3 I (pu) TM3 Test Mode 3. Do not overdrive default value during reset.
Table 16. Pin Definitions—I/O Strap Pins (Continued)
Signal
Type (at
Reset) On Pin … Description
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Table 17. Strap Pin Internal Resistors—Active Reset
(RST_IN
= 0) vs. Normal Operation (RST_IN = 1)
Pin RST_IN = 0 RST_IN = 1
BMS
(pd_0) (pu_0)
BM
(pd) Driven
TMR0E (pd) Driven
BUSLOCK (pd_0) (pu_0)
L1BCMPO
(pu) Driven
TM2 (pu) Driven
TM3 (pu) Driven
pd = internal pull-down 5 k; pu = internal pull-up 5 k;
pd_0 = internal pull-down 5 k on processor ID = 0;
pu_0 = internal pull-up 5 k on processor ID = 0