Datasheet

Rev. D | Page 18 of 48 | May 2012
ADSP-TS203S
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
processor operating modes. During reset, the processor samples
the strap option pins. Strap pins have an internal pull-up or
pull-down for the default value. If a strap pin is not connected to
an overdriving external pull-up, pull-down, or logic load, the
processor samples the default value during reset. If strap pins
are connected to logic inputs, a stronger external pull-up or
pull-down may be required to ensure default value depending
on leakage and/or low level input current of the logic load. To
set a mode other than the default mode, connect the strap pin to
a sufficiently stronger external pull-up or pull-down. Table 16
lists and describes each of the processor’s strap pins.
Table 15. Pin Definitions—Power, Ground, and Reference
Signal Type Term Description
V
DD
PnaV
DD
pins for internal logic.
V
DD_A
PnaV
DD
pins for analog circuits. Pay critical attention to bypassing this supply.
V
DD_IO
PnaV
DD
pins for I/O buffers.
V
DD_DRAM
PnaV
DD
pins for internal DRAM.
V
REF
I na Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN,
POR_IN
, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,
LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. V
REF
can be
connected to a power supply or set by a voltage divider circuit as shown in Figure 4.
For more information, see Filtering Reference Voltage and Clocks on Page 8.
SCLK_V
REF
I na System Clock Reference. Connect this pin to a reference voltage as shown in
Figure 5. For more information, see Filtering Reference Voltage and Clocks on
Page 8.
V
SS
GnaGround pins.
NC — nc No Connect. Do not connect these pins to anything (not to any supply, signal, or
each other). These pins are reserved and must be left unconnected.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS
Table 16. Pin Definitions—I/O Strap Pins
Signal
Type (at
Reset) On Pin … Description
EBOOT I (pd_0) BMS
EPROM Boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot processor through the
external port or a link port
IRQEN I (pd) BM Interrupt Enable.
0 = disable and set IRQ3–0
interrupts to edge-sensitive after reset (default)
1 = enable and set IRQ3–0
interrupts to level-sensitive immediately after reset
LINK_DWIDTH I (pd) TMR0E Link Port Input Default Data Width.
0 = 1-bit (default)
1 = 4-bit
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.