Datasheet

Rev. D | Page 16 of 48 | May 2012
ADSP-TS203S
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal Type Term Description
FLAG3–0 I/O/A
(pu)
nc FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
can be configured individually for input or for output. FLAG3–0 are inputs after power-
up and reset.
IRQ3–0
I/A
(pu)
nc Interrupt Request. When asserted, the processor generates an interrupt. Each of the
IRQ3–0
pins can be independently set for edge-triggered or level-sensitive operation.
After reset, these pins are disabled unless the IRQ3–0 strap option and interrupt vectors
are initialized for booting.
TMR0E O na Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
For more information, see Table 16 on Page 18.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS
Table 11. Pin Definitions—Link Ports
Signal Type Term Description
LxDATO3–0P O nc Link Ports 1–0 Data 1–0 Transmit LVDS P
LxDATO3–0N O nc Link Ports 1–0 Data 1–0 Transmit LVDS N
LxCLKOUTP O nc Link Ports 1–0 Transmit Clock LVDS P
LxCLKOUTN O nc Link Ports 1–0 Transmit Clock LVDS N
LxACKI I (pd) nc Link Ports 1–0 Receive Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPO
O (pu) nc Link Ports 1–0 Block Completion. When the transmission is executed using DMA,
this signal indicates to the receiver that the transmitted block is completed. The
pull-up resistor is present on L0BCMPO
only. At reset, the L1BCMPO pin is a strap
pin. For more information, see Table 16 on Page 18.
LxDATI3–0P I V
DD_IO
Link Ports 1–0 Data 3–0 Receive LVDS P
LxDATI3–0N I V
DD_IO
Link Ports 1–0 Data 3–0 Receive LVDS N
LxCLKINP I/A V
DD_IO
Link Ports 1–0 Receive Clock LVDS P
LxCLKINN I/A V
DD_IO
Link Ports 1–0 Receive Clock LVDS N
LxACKO O nc Link Ports 1–0 Transmit Acknowledge. Using this signal, the receiver indicates to the
transmitter that it may continue the transmission.
LxBCMPI
I (pd_l) V
SS
Link Ports 1–0 Block Completion. When the reception is executed using DMA, this
signal indicates to the receiver that the transmitted block is completed.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS