Datasheet

Rev. D | Page 14 of 48 | May 2012
ADSP-TS203S
Table 7. Pin Definitions—External Port DMA/Flyby
Signal Type Term Description
DMAR3–0
I/A epu DMA Request Pins. Enable external I/O devices to request DMA services from the
processor. In response to DMARx, the processor performs DMA transfers according
to the DMA channel’s initialization. The processor ignores DMA requests from unini-
tialized channels.
IOWR O/T
(pu_0)
nc I/O Write. When a processor DMA channel initiates a flyby mode read transaction,
the processor asserts the IOWR signal during the data cycles. This assertion makes
the I/O device sample the data instead of the TigerSHARC.
IORD
O/T
(pu_0)
nc I/O Read. When a processor DMA channel initiates a flyby mode write transaction,
the processor asserts the IORD
signal during the data cycle. This assertion with the
IOEN makes the I/O device drive the data instead of the TigerSHARC.
IOEN
O/T
(pu_0)
nc I/O Device Output Enable. Enables the output buffers of an external I/O device for
fly-by transactions between the device and external memory. Active on flyby
transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS
Table 8. Pin Definitions—External Port SDRAM Controller
Signal Type Term Description
MSSD3–0
I/O/T
(pu_0)
nc Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
processor accesses SDRAM memory space. MSSD3–0
are decoded memory address
pins that are asserted whenever the processor issues an SDRAM command cycle
(access to ADDR31:30 = 0b01—except reserved spaces shown in Figure 2 on
Page 6). In a multiprocessor system, the master processor drives MSSD3–0
.
RAS
I/O/T
(pu_0)
nc Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
CAS
I/O/T
(pu_0)
nc Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
LDQM O/T
(pu_0)
nc Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when CAS
is asserted, and inactive
on read transactions.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS