Datasheet

ADSP-TS203S
Rev. D | Page 13 of 48 | May 2012
Table 6. Pin Definitions—External Port Arbitration
Signal Type Term Description
BR7–0
I/O V
DD_IO
1
Multiprocessing Bus Request Pins. Used by the processors in a multiprocessor
system to arbitrate for bus mastership. Each processor drives its own BRx line (corre-
sponding to the value of its ID2–0 inputs) and monitors all others. In systems with
fewer than eight processors, set the unused BRx
pins high (V
DD_IO
).
ID2–0 I (pd) na Multiprocessor ID. Indicates the processor’s ID, from which the processor deter-
mines its order in a multiprocessor system. These pins also indicate to the processor
which bus request (BR0
–BR7) to assert when requesting the bus: 000 = BR0,
001 = BR1
, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7.
ID2–0 must have a constant value during system operation and can change during
reset only.
BM
O na Bus Master. The current bus master processor asserts BM. For debugging only. At
reset this is a strap pin. For more information, see Table 16 on Page 18.
BOFF
I epu Back Off. A deadlock situation can occur when the host and a processor try to read
from each other’s bus at the same time. When deadlock occurs, the host can assert
BOFF
to force the processor to relinquish the bus before completing its outstanding
transaction.
BUSLOCK
O/T
(pu_0)
na Bus Lock Indication. Provides an indication that the current bus master has locked
the bus. At reset, this is a strap pin. For more information, see Table 16 on Page 18.
HBR
I epu Host Bus Request. A host must assert HBR to request control of the processor’s
external bus. When HBR
is asserted in a multiprocessing system, the bus master
relinquishes the bus and asserts HBG once the outstanding transaction is finished.
HBG
I/O/T
(pu_0)
epu
2
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master processor three-states the
ADDR31–0, DATA31–0, MSH
, MSSD3–0, MS1–0, RD, WRL, BMS, BRST, IORD, IOWR,
IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and TM4 pins, and the processor puts
the SDRAM in self-refresh mode. The processor asserts HBG until the host deasserts
HBR
. In multiprocessor systems, the current bus master processor drives HBG, and
all slave processors monitor it.
CPA
I/O/OD
(pu_od_0)
epu
2
Core Priority Access. Asserted while the processor’s core accesses external memory.
This pin enables a slave processor to interrupt a master processor’s background
DMA transfers and gain control of the external bus for core-initiated transactions.
CPA
is an open-drain output, connected to all DSPs in the system. If not required in
the system, leave CPA unconnected (external pull-ups will be required for processor
ID = 1 through ID = 7).
DPA
I/O/OD
(pu_od_0)
epu
2
DMA Priority Access. Asserted while a high priority processor DMA channel accesses
external memory. This pin enables a high priority DMA channel on a slave processor
to interrupt transfers of a normal priority DMA channel on a master processor and
gain control of the external bus for DMA-initiated transactions. DPA
is an open-drain
output, connected to all DSPs in the system. If not required in the system, leave DPA
unconnected (external pull-ups will be required for processor ID = 1 through
ID = 7).
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS
1
The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V
DD_IO
.
2
This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.