Datasheet

ADSP-TS203S
Rev. D | Page 11 of 48 | May 2012
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS203S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the ac
specification for asynchronous signals when the system design
requires predictable, cycle-by-cycle behavior for these signals.
The output pins can be three-stated during normal operation.
The processor three-states all output during reset, allowing
these pins to get to their internal pull-up or pull-down state.
Some pins have an internal pull-up or pull-down resistor (±30%
tolerance) that maintains a known value during transitions
between different drivers.
Table 3. Pin Definitions—Clocks and Reset
Signal Type Term Description
SCLKRAT2–0 I (pd) na Core Clock Ratio. The processor’s core clock (CCLK) rate = n × SCLK, where n is user-
programmable using the SCLKRATx pins to the values shown in Table 4. These pins
may change only during reset; connect these pins to V
DD_IO
or V
SS
. All reset specifi-
cations in Table 25, Table 26, and Table 27 must be satisfied. The core clock rate
(CCLK) is the instruction cycle rate.
SCLK I na System Clock Input. The processor’s system input clock for cluster bus. The core
clock rate is user-programmable using the SCLKRATx pins. For more information,
see Clock Domains on Page 8.
RST_IN
I/A na Reset. Sets the processor to a known state and causes program to be in idle state.
RST_IN must be asserted a specified time according to the type of reset operation.
For details, see Reset and Booting on Page 8, Table 27 on Page 26, and Figure 12 on
Page 26.
RST_OUT
O na Reset Output. Indicates that the processor reset is complete. Connect to POR_IN.
POR_IN
I/A na Power-On Reset for internal DRAM. Connect to RST_OUT.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k; pu = internal pull-up 5 k; pd_0 = internal pull-down 5 k on processor ID = 0; pu_0 = internal pull-up 5 k on processor ID = 0;
pu_od_0 = internal pull-up 500  on processor ID = 0; pd_m = internal pull-down 5 k on processor bus master; pu_m = internal pull-up
5 k on processor bus master; pu_ad = internal pull-up 40 k. For more pull-down and pull-up information, see Electrical Characteristics
on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k to V
SS
; epu = external pull-up
approximately 5 k to V
DD_IO
, nc = not connected; na = not applicable (always used); V
DD_IO
= connect directly to V
DD_IO
; V
SS
= connect
directly to V
SS
Table 4. SCLK Ratio
SCLKRAT2–0 Ratio
000 (default) 4
001 5
010 6
011 7
100 8
101 10
110 12
111 Reserved