Datasheet

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
TigerSHARC
Embedded Processor
ADSP-TS203S
Rev. D
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KEY FEATURES
500 MHz, 2.0 ns instruction cycle rate
4M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid array
package
Dual-computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual-integer ALUs, providing data addressing and pointer
manipulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
Integrated I/O includes 10-channel DMA controller, external
port, two link ports, SDRAM controller, programmable flag
pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for large, demanding
multiprocessor DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in Table 1)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other (multiprocessor)
DSPs
Eases programming through extremely flexible instruction
set and high-level-language-friendly architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Figure 1. Functional Block Diagram
T
L0
4
8
4
8
4
8
4
8
4
IN
OUT
HOST
MULTI-
PROC
C-BUS
ARB
DATA
32
LINK PORTS
JTAG PORT
EXTERNAL
PORT
ADDR
32
6
SOC BUS
DMA
JTAG
SDRAM
CTRL
EXT DMA
REQ
J-BUS DATA
IAB
PC
BTB
ADDR
FETCH
PROGRAM
SEQUENCER
COMPUTATIONAL BLOCKS
J-BUS ADDR
K-BUS DATA
K-BUS ADDR
I-BUS DATA
I-BUS ADDR
S-BUS DATA
S-BUS ADDR
INTEGER
KALU
INTEGER
JALU
32
32
32-BIT × 32-BIT
DATA ADDRESS GENERATION
X
REGISTER
FILE
32-BIT × 32-BIT
MULALUSHIFT
DAB
128
128
DAB
128
128
MEMORY BLOCKS
A
D
4M BITS INTERNAL MEMORY
4 × CROSSBAR CONNECT
(PAGE CACHE)
A
D
A
D
A
D
SOC
I/F
Y
REGISTER
FILE
32-BIT × 32-BIT
MUL ALU SHIFT
L1
IN
OUT
CTRL
8
CTRL
10
32
128
32
128
32
128
21
128
4
32-BIT × 32-BIT