Datasheet

Rev. C | Page 6 of 48 | December 2006
ADSP-TS202S
EXTERNAL PORT (OFF-CHIP
MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS202S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G bytes per
second over the external bus.
The external bus can be configured for 32-bit or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS202S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS202S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for
Figure 3. ADSP-TS202S Memory Map
RESERVED
RE SE RV ED
INTERNAL REG ISTERS (UREGS)
INTERNAL MEMORY BLOCK 4
INTERNAL MEMORY BLOCK 2
INTERNAL MEMORY BLOCK 0
0x 03 FFFFFF
0x001E0000
0x 001 E0 3FF
0x000CFFFF
0x 00 0C0 000
0x0008FFFF
0x0 00 80 000
0x0004FFFF
0x0 00 40 000
0x0000FFFF
0x0 00 00 000
INTERNAL SPACE
PROCES SOR I D 7
PROCES SOR I D 6
PROCES SOR I D 5
PROCES SOR I D 4
PROCES SOR I D 3
PROCES SOR I D 2
PROCES SOR I D 1
PROCES SOR I D 0
BROADCAST
HO ST ( MSH)
BANK 1 (MS 1)
BANK 0 (MS 0)
MSSD BANK 0 ( MSSD0)
INTERNAL MEMORY
0x 50 00 0000
0x4 00 00 000
0x 38 00 0000
0x 300 00 000
0x 2C0000 00
0x 280 00 000
0x 240 00 000
0x 200 00 000
0x 1C0000 00
0x 180 00 000
0x 140 00 000
0x 100 00 000
0x 0C0000 00
0x 03 FF FFFF
0x 000 00 000
GLO BAL SPACE
0 xFFFFFFFF
M
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A
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M
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M
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P
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C
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EA CH IS A COPY
OF INTERNAL SPACE
RESERVED
INTERNAL MEMORY BLOCK 6
I NTERNAL MEMORY BLOCK 8
0x0010FFFF
0x0 01 00 000
INTERNAL MEMORY BLOCK 1 0
0x0014FFFF
0x0 01 40 000
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SOC RE GISTE R S (UREGS)
0x001F0000
0x 00 1F0 3FF
MSSD BANK 1 ( MSSD1)
MSSD BANK 2 (MSSD2 )
MSSD BANK 3 ( MSSD3)
0x 60 00 0000
0x 70 00 0000
0x 80 00 0000
RES ERV ED
RES ERV ED
RES ERV ED
RES ERV ED
0x 54 00 0000
0x4 40 00 000
0x 64 00 0000
0x 74 00 0000