Datasheet

Rev. C | Page 42 of 48 | May 2009
ADSP-TS101S
AA1 DATA46 AB1 DATA49 AC1 V
SS
AD1 V
SS
AE1 V
SS
AA2 DATA45 AB2 DATA48 AC2 V
SS
AD2 V
SS
AE2 V
SS
AA3 DATA44 AB3 DATA47 AC3 DATA50 AD3 V
SS
AE3 V
SS
AA4 V
DD_IO
AB4 V
DD_IO
AC4 DATA51 AD4 DATA52 AE4 DATA53
AA5 V
DD_IO
AB5 V
DD_IO
AC5 DATA54 AD5 DATA55 AE5 DATA56
AA6 V
DD_IO
AB6 V
DD_IO
AC6 DATA57 AD6 DATA58 AE6 DATA59
AA7 V
DD
AB7 V
DD_IO
AC7 DATA60 AD7 DATA61 AE7 DATA62
AA8 V
DD
AB8 V
DD_IO
AC8 DATA63 AD8 L2DAT0 AE8 L2DAT1
AA9 V
DD_IO
AB9 V
DD_IO
AC9 L2DAT2 AD9 L2DAT3 AE9 L2DAT4
AA10 V
DD_IO
AB10 V
DD_IO
AC10 L2DAT5 AD10 L2DAT6 AE10 L2DAT7
AA11 V
DD
AB11 V
DD_IO
AC11 L2CLKOUT AD11 L2CLKIN AE11 L2DIR
AA12 V
DD
AB12 V
DD_IO
AC12 NC AD12 BR0 AE12 BR1
AA13 V
DD_IO
AB13 V
DD_IO
AC13 BR2 AD13 BR3 AE13 BR4
AA14 V
DD_IO
AB14 V
DD_IO
AC14 BR5 AD14 BR6 AE14 BR7
AA15 V
DD
AB15 V
DD_IO
AC15 ACK AD15 HBR AE15 BOFF
AA16 V
DD
AB16 V
DD_IO
AC16 HBG AD16 CPA AE16 DPA
AA17 V
DD_IO
AB17 V
DD_IO
AC17 ADDR0 AD17 ADDR1 AE17 ADDR2
AA18 V
DD_IO
AB18 V
DD_IO
AC18 ADDR3 AD18 ADDR4 AE18 ADDR5
AA19 V
DD
AB19 V
DD_IO
AC19 ADDR6 AD19 ADDR7 AE19 ADDR8
AA20 V
DD
AB20 V
DD_IO
AC20 ADDR9 AD20 SDA10 AE20 ADDR10
AA21 V
DD_IO
AB21 V
DD_IO
AC21 ADDR11 AD21 ADDR12 AE21 ADDR13
AA22 V
DD_IO
AB22 V
DD_IO
AC22 ADDR14 AD22 ADDR15 AE22 V
SS
AA23 ADDR23 AB23 ADDR20 AC23 V
SS
AD23 V
SS
AE23 V
SS
AA24 ADDR22 AB24 ADDR19 AC24 ADDR17 AD24 V
SS
AE24 V
SS
AA25 ADDR21 AB25 ADDR18 AC25 ADDR16 AD25 V
SS
AE25 V
SS
Figure 42. 625-Ball PBGA Pin Configurations (Top View, Summary)
Table 36. 625-Ball (27 mm  27 mm) PBGA Pin Assignments (Continued)
Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic
TOP VIEW
19
17 21
23
25
15
13119
57
31
20
18
1614
1210
8624
22
24
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Y
W
V
U
T
AE
AD
AC
AB
AA
V
DD
V
DD_IO
V
SS
SIGNAL
V
DD_A
V
SS_A
KEY: