Datasheet

Rev. C | Page 34 of 48 | May 2009
ADSP-TS101S
TEST CONDITIONS
The test conditions for timing parameters appearing in Table 29
on Page 29 and Table 30 on Page 30 include output disable time,
output enable time, and capacitive loading. The timing specifi-
cations for the DSP apply for the voltage reference levels in
Figure 29.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the fol-
lowing equation:
The output disable time t
DIS
is the difference between
t
MEASURED_DIS
and t
DECAY
as shown in Figure 30. The time
t
MEASURED_DIS
is the interval from when the reference signal
switches to when the output voltage decays V from the mea-
sured output high or output low voltage. The t
DECAY
value is
calculated with test loads C
L
and I
L
, and with V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by
 V is
dependent on the capacitive load, C
L
, and the drive current, I
D
.
This ramp time can be approximated by the following equation:
The output enable time t
ENA
is the difference between
t
MEASURED_ENA
and t
RAMP
as shown in Figure 30. The time
t
MEASURED_ENA
is the interval from when the reference signal
switches to when the output voltage ramps V from the mea-
sured three-stated output level. The t
RAMP
value is calculated
with test load C
L
, drive current I
D
, and with V equal to 0.5 V.
Capacitive Loading
Figure 31 shows the circuit with variable capacitance that is
used for measuring typical output rise and fall times. Figure 32
through Figure 39 show how output rise time varies with capac-
itance. Figure 40 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 34.) The graphs of Figure 32 through Figure 40 may not be
linear outside the ranges shown.
Figure 29. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Figure 30. Output Enable/Disable
INPUT
OR
OUTPUT
1.5V 1.5V
REFERENCE
SIGNAL
t
DIS
OUTPUT S TARTS
DRIVING
V
OH (MEASURED)
– ⌬V
V
OL (M EASURED)
+ ⌬V
t
MEASURED_DIS
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VO LTAG E TO BE APPROXIMATELY 1 .5V.
OUTPUT STOPS
DRIVING
t
DECAY
t
ENA
t
MEASURED_ENA
t
RAMP
t
DECAY
C
L
V
I
L
---------------
=
Figure 31. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 32. Typical Output Rise and Fall Time (10%–90%, V
DD_IO
=3.3V)
vs. Load Capacitance at Strength 0
t
RAMP
C
L
V
I
D
---------------
=
1.5V
TO
OUTPUT
PIN
VARIABLE
(10 pF to 100pF)
0
10 20 30 40 50 60 70 80 90 100
0
5
10
15
20
25
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
LOAD CAPACITANCE (pF)
RISE TIME
y = 0.2015x + 3.8869
FALL TIME
y = 0.174x + 2 .6931
STRENGTH 0
(V
DD_IO
=3.3V)