Datasheet

Rev. C | Page 30 of 48 | May 2009
ADSP-TS101S
Table 30. Link Ports—Receive
Parameter Min Max Unit
Timing Requirements
t
L X CLK_R X
1, 2
Receive Link Clock Period 0.9  LR  t
CCLK
1.1  LR  t
CCLK
ns
t
L X CLKH_R X
3
Receive Link Clock Width High 0.33  t
L X CLK_R X
0.66  t
L X CLK_R X
ns
t
L X CLKH_R X
4
Receive Link Clock Width High 0.4  t
L X CLK_R X
0.6  t
L X CLK_R X
ns
t
L X CLKL_R X
3
Receive Link Clock Width Low 0.33  t
L X CLK_R X
0.66  t
L X CLK_R X
ns
t
L X CLKL_R X
4
Receive Link Clock Width Low 0.4  t
L X CLK_R X
0.6  t
L X CLK_R X
ns
t
DIS
LxDAT7–0 Input Setup 0.6 ns
t
DIH
LxDAT7–0 Input Hold 0.6 ns
Switching Characteristics
t
CONNV
Connectivity Pulse Valid 0 2.5  t
L X CLK_R X
ns
t
CONNOW
Connectivity Pulse Output Width 1.5  t
L X CLK_R X
ns
1
The link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
2
The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK  250 MHz.
3
The formula for this parameter applies when LR is 2.
4
The formula for this parameter applies when LR is 3, 4, or 8.
Figure 18. Link Ports—Receive
LxCLKIN
LxCLKOUT
LxDAT7–0
LxDIR
1
2
3
4
5
6
7
80
9
10
11
12
13
14
15
t
LxCLK_Rx
t
CONNV
t
LxCLKH_Rx
t
LxCLKL_Rx
t
CONNOW
t
DIS
t
DIH
t
DIS
t
DIH