Datasheet

ADSP-TS101S
Rev. C | Page 29 of 48 | May 2009
Link Ports Data Transfer and Token Switch Timing
Table 31, Table 32, Table 33, and Table 34 with Figure 17,
Figure 18, Figure 19, and Figure 20 provide the timing specifica-
tions for the link ports data transfer and token switch.
Table 29. Link Ports—Transmit
Parameter Min Max Unit
Timing Requirements
t
CONNS
1
Connectivity Pulse Setup 2  t
CCLK
+ 3.5 ns
t
CONNS
2
Connectivity Pulse Setup 8 ns
t
CONNIW
3
Connectivity Pulse Input Width t
L X CLK_T X
+ 1 ns
t
ACKS
Acknowledge Setup 0.5  t
L X CLK_T X
ns
Switching Characteristics
t
L X CLK_T X
4
Transmit Link Clock Period 0.9  LR  t
CCLK
1.1  LR  t
CCLK
ns
t
L X CLKH_T X
1
Transmit Link Clock Width High 0.33  t
L X CLK_T X
0.66  t
L X CLK_T X
ns
t
L X CLKH_T X
2
Transmit Link Clock Width High 0.4  t
L X CLK_T X
0.6  t
L X CLK_T X
ns
t
L X CLKL_T X
1
Transmit Link Clock Width Low 0.33  t
L X CLK_T X
0.66  t
L X CLK_T X
ns
t
L X CLKL_T X
2
Transmit Link Clock Width Low 0.4  t
L X CLK_T X
0.6  t
L X CLK_T X
ns
t
DIRS
LxDIR Transmit Setup 0.5  t
L X CLK_T X
2  t
L X CLK_T X
ns
t
DIRH
LxDIR Transmit Hold 0.5  t
L X CLK_T X
2  t
L X CLK_T X
ns
t
DOS
1
LxDAT7–0 Output Setup 0.25  t
L X CLK_T X
– 1 ns
t
DOH
1
LxDAT7–0 Output Hold 0.25  t
L X CLK_T X
– 1 ns
t
DOS
2
LxDAT7–0 Output Setup Greater of 0.8 or 0.17  t
L X CLK_T X
– 1 ns
t
DOH
2
LxDAT7–0 Output Hold Greater of 0.8 or 0.17  t
L X CLK_T X
– 1 ns
t
LDOE
LxDAT7–0 Output Enable 1 ns
t
LDOD
5
LxDAT7–0 Output Disable 1 ns
1
The formula for this parameter applies when LR is 2.
2
The formula for this parameter applies when LR is 3, 4, or 8.
3
LxCLKIN shows the connectivity pulse with each of the three possible transitions to “Acknowledge.” After a connectivity pulse low minimum, LxCLKIN may [1] return high
and remain high for “Acknowledge,” [2] return high and subsequently go low (meeting t
ACKS
) for “Not Acknowledge,” or [3] remain low for “Not Acknowledge.”
4
The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register. The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK  250 MHz.
5
This specification applies to the last data byte or the “Dummy” byte that follows the verification byte if enabled. For more information, see the ADSP-TS101 TigerSHARC
Processor Hardware Reference.
Figure 17. Link Ports—Transmit
LxCLKOUT
LxCLKIN
LxDIR
LxDAT7–0
1
2
3
40
5
6
7
8
9
10
11
12
13
14
15
t
LxCLKL_Tx
t
LxCLKH_Tx
t
DIRS
t
LxCLK_Tx
t
CONNS
t
DOS
t
DOH
t
DOS
t
ACKS
t
DOH
t
CON N IW
t
DIRH
t
LDOD
t
LDOE