Datasheet

ADSP-TS101S
Rev. C | Page 27 of 48 | May 2009
RESET
4, 7
Global Reset SCLK
TMS
4
Test Mode Select (JTAG) 1.5 1.0 TCK
TDI
4
Test Data Input (JTAG) 1.5 1.0 TCK
TDO Test Data Output (JTAG) 6.0 1.0 1.0 5.0 TCK_FE
8
TRST
4, 7, 9
Test Reset (JTAG) TCK
BM
5
Bus Master Debug Aid Only 4.2 0.8 SCLK
EMU
10
Emulation 5.5 5.0 TCK or LCLK
JTAG_SYS_IN
11
System Input 1.5 11.0 TCK
JTAG_SYS_OUT
12
System Output 16.0 TCK_FE
8
ID2–0
9
Chip ID—Must Be Constant
CONTROLIMP2–0
9
Static Pins—Must Be Constant
DS2–0
9
Static Pins—Must Be Constant
LCLKRAT2–0
9
Static Pins—Must Be Constant
SCLKFREQ
9
Static Pins—Must Be Constant
1
The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive loading, see Figure 40
on Page 36.
2
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
3
CPA and DPA pins are open drains and have 0.5 k internal pull-ups.
4
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for recognition in the
current clock reference cycle.
5
This pin is a strap option. During reset, an internal resistor pulls the pin low.
6
For input specifications, see Table 21.
7
For additional requirement details, see Reset and Booting on Page 9.
8
TCK_FE indicates TCK falling edge.
9
These pins may change only during reset; recommend connecting it to V
DD_IO
/V
SS
.
10
Reference clock depends on function.
11
System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31–0,
DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN, L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0,
CONTROLIMP2–0, RESET
, DMAR3–0.
12
System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS,
ADDR31–0, DATA63–0, DPA
, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0, L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT,
L3DAT7–0, L3DIR, EMU.
Table 28. AC Signal Specifications (for 16.7 ns <SCLK <25 ns) (All values in this table are in nanoseconds) (Continued)
Name Description Input Setup (min) Input Hold (min) Output Valid (max)
1
Output Hold (min) Output Enable (min)
2
Output Disable (max)
2
Reference Clock