Datasheet

ADSP-TS101S
Rev. C | Page 25 of 48 | May 2009
Table 27. AC Signal Specifications (for SCLK <16.7 ns) (All values in this table are in nanoseconds)
Name Description Input Setup (min) Input Hold (min) Output Valid (max)
1
Output Hold (min) Output Enable (min)
2
Output Disable (max)
2
Reference Clock
ADDR31–0 External Address Bus 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
DATA63–0 External Data Bus 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
MSH
Memory Select Host Line 4.2 1.0 0.9 2.5 SCLK
MSSD
Memory Select SDRAM Line 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
MS1–0
Memory Select for Static Blocks 4.2 1.0 0.9 2.5 SCLK
RD
Memory Read 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
WRL
Write Low Word 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
WRH
Write High Word 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
ACK Acknowledge for Data 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
SDCKE SDRAM Clock Enable 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
RAS
Row Address Select 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
CAS
Column Address Select 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
SDWE
SDRAM Write Enable 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
LDQM Low Word SDRAM Data Mask 4.2 1.0 0.9 2.5 SCLK
HDQM High Word SDRAM Data Mask 4.2 1.0 0.9 2.5 SCLK
SDA10 SDRAM ADDR10 4.2 1.0 0.9 2.5 SCLK
HBR
Host Bus Request 2.6 0.5 SCLK
HBG
Host Bus Grant 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
BOFF
Back Off Request 2.6 0.5 SCLK
BUSLOCK
Bus Lock 4.2 1.0 0.9 2.5 SCLK
BRST
Burst Access 2.6 0.5 4.2 1.0 0.9 2.5 SCLK
BR7–0
Multiprocessing Bus Request 2.6 0.5 4.2 1.0 SCLK
FLYBY
Flyby Mode Selection 4.2 1.0 0.9 2.5 SCLK
IOEN
Flyby I/O Enable 4.2 1.0 0.9 2.5 SCLK
CPA
3, 4
Core Priority Access 2.6 0.5 5.8 2.5 SCLK
DPA
3, 4
DMA Priority Access 2.6 0.5 5.8 2.5 SCLK
BMS
5
Boot Memory Select 4.2 1.0 0.9 2.5 SCLK
FLAG3–0
6
FLAG Pins 4.2 1.0 1.0 4.0 SCLK
RESET
4, 7
Global Reset SCLK
TMS
4
Test Mode Select (JTAG) 1.5 1.0 TCK
TDI
4
Test Data Input (JTAG) 1.5 1.0 TCK
TDO Test Data Output (JTAG) 6.0 1.0 1.0 5.0 TCK_FE
8
TRST
4, 7, 9
Test Reset (JTAG) TCK
BM
5
Bus Master Debug Aid Only 4.2 1.0 SCLK
EMU
10
Emulation 5.5 5.0 TCK or LCLK
JTAG_SYS_IN
11
System Input 1.5 11.0 TCK
JTAG_SYS_OUT
12
System Output 16.0 TCK_FE
8
ID2–0
9
Chip ID—Must Be Constant
CONTROLIMP2–0
9
Static Pins—Must Be Constant
DS2–0
9
Static Pins—Must Be Constant
LCLKRAT2–0
9
Static Pins—Must Be Constant
SCLKFREQ
9
Static Pins—Must Be Constant