Datasheet

Rev. C | Page 24 of 48 | May 2009
ADSP-TS101S
Table 25. Power-Up Reset Timing
Parameter Min Max Unit
Timing Requirements
t
START_LO
RESET Deasserted After V
DD
, V
DD_A
, V
DD_IO
, SCLK/LCLK, and
Static/Strap Pins Are Stable and Within Specification
2ms
t
PULSE1_HI
RESET Deasserted for First Pulse 50  t
SCLK
100  t
SCLK
ns
t
PULSE2_LO
RESET Asserted for Second Pulse 100  t
SCLK
ns
t
TRST_PWR
1
TRST Asserted During Power-Up Reset 2  t
SCLK
ns
1
Applies after V
DD
, V
DD_A
, V
DD_IO
, and SCLK/LCLK and static/strap pins are stable and within specification, and before RESET is deasserted.
Figure 14. Power-Up Reset Timing
Table 26. Normal Reset Timing
Parameter Min Max Unit
Timing Requirements
t
RST_IN
RESET Asserted 100  t
SCLK
ns
t
STRAP
RESET Deasserted After Strap Pins Stable 2 ms
Figure 15. Normal Reset (Hot Reset) Timing
RESET
TRST
t
TRST_PWR
t
START_LO
V
DD,
V
DD_A,
V
DD_IO,
SCLK /L C LK,
S TA TIC /ST RA P
PINS
t
PULSE1_HI
t
PULSE2_LO
RESET
STRAP PINS
t
RST_IN
t
STRAP