Datasheet

ADSP-TS101S
Rev. C | Page 23 of 48 | May 2009
Table 22. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter Description Min Max Unit
t
SCLK
1,
2,
3,
4
System Clock Cycle Time 10 25 ns
t
SCLKH
System Clock Cycle High Time 0.4 × t
SCLK
0.6 × t
SCLK
ns
t
SCLKL
System Clock Cycle Low Time 0.4 × t
SCLK
0.6 × t
SCLK
ns
t
SCLKJ
5,
6
System Clock Jitter Tolerance 500 ps
1
For more information, see Table 3 on Page 12.
2
For more information, see Clock Domains on Page 9.
3
LCLK_P and SCLK_P must be connected to the same source.
4
The value of (t
SCLK
/ LCLKRAT2-0) must not violate the specification for t
CCLK
.
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 11. Reference Clocks—System Clock (SCLK) Cycle Time
Table 23. Reference Clocks—Test Clock (TCK) Cycle Time
Parameter Description Min Max Unit
t
TCK
Test Clock (JTAG) Cycle Time Greater of 30 or t
CCLK
× 4 ns
t
TCKH
Test Clock (JTAG) Cycle High Time 12.5 ns
t
TCKL
Test Clock (JTAG) Cycle Low Time 12.5 ns
Figure 12. Reference Clocks—Test Clock (TCK) Cycle Time
Table 24. Power-Up Timing
1
Parameter Min Max Unit
Timing Requirement
t
VDD_IO
V
DD_IO
Stable and Within Specification After V
DD
and V
DD_A
Are Stable and Within Specification
>0 ms
1
For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.
Figure 13. Power-Up Sequencing Timing
SCLK_P
t
SCLK
t
SCLKH
t
SCLKL
t
SCLKJ
SCLK_P
t
SCLK
t
SCLKH
t
SCLKL
t
SCLKJ
TCK
t
TCK
t
TCKH
t
TCKL
V
DD
V
DD_A
V
DD_IO
t
VDD_IO