Datasheet

Rev. C | Page 22 of 48 | May 2009
ADSP-TS101S
For power-up sequencing, power-up reset, and normal reset
(hot reset) timing requirements, refer to Table 26 and Figure 13,
Table 27 and Figure 14, and Table 28, and Figure 15
respectively.
Table 19. AC Asynchronous Signal Specifications (All values in this table are in nanoseconds)
Name Description Pulse Width Low (min) Pulse Width High (min)
IRQ3–0
1
Interrupt request input t
CCLK
+ 3 ns
DMAR3–0
1
DMA request input t
CCLK
+ 4 ns t
CCLK
+ 4 ns
TMR0E
2
Timer 0 expired output 4  t
SCLK
ns
FLAG3–0
1, 3
Flag pins input 3  t
CCLK
ns 3  t
CCLK
ns
TRST
JTAG test reset input 1 ns
1
These input pins do not need to be synchronized to a clock reference.
2
This pin is a strap option. During reset, an internal resistor pulls the pin low.
3
For output specifications, see Table 29 and Table 30.
Table 20. Reference Clocks—Core Clock (CCLK) Cycle Time
Parameter Description
Grade = 100 (300 MHz) Grade = 000 (250 MHz)
UnitMin Max Min Max
t
CCLK
1
Core Clock Cycle Time 3.3 12.5 4.0 12.5 ns
1
CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t
SCLK
) divided by the system clock ratio
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 45.
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
Table 21. Reference Clocks—Local Clock (LCLK) Cycle Time
Parameter Description Min Max Unit
t
LCLK
1, 2, 3, 4
Local Clock Cycle Time 10 25 ns
t
LCLKH
Local Clock Cycle High Time 0.4 × t
LCLK
0.6 × t
LCLK
ns
t
LCLKL
Local Clock Cycle Low Time 0.4 × t
LCLK
0.6 × t
LCLK
ns
t
LCLKJ
5,
6
Local Clock Jitter Tolerance 500 ps
1
For more information, see Table 3 on Page 12.
2
For more information, see Clock Domains on Page 9.
3
LCLK_P and SCLK_P must be connected to the same source.
4
The value of (t
LCLK
/ LCLKRAT2-0) must not violate the specification for t
CCLK
.
5
Actual input jitter should be combined with ac specifications for accurate timing analysis.
6
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 10. Reference Clocks—Local Clock (LCLK) Cycle Time
CCLK
t
CCLK
LCLK_P
t
LCLK
t
LCLKH
t
LCLKL
t
LCLKJ
LCLK_P
t
LCLK
t
LCLKH
t
LCLKL
t
LCLKJ