Datasheet

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
TigerSHARC
Embedded Processor
ADSP-TS101S
Rev. C
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FEATURES
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
BENEFITS
Provides high performance Static Superscalar DSP opera-
tions, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O bench-
marks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruc-
tion set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
Figure 1. Functional Block Diagram
L1
3
8
L2
8
3
L3
3
8
INPUT FIFO
OUTPUT BUFFER
OUTPUT FIFO
HOST INTERFACE
MULTIPROCESSOR
INTERFACE
CLUSTER BUS
ARBITER
DATA
64
LINK
PORTS
JTAG PORT
SDRAM CONTROLLER
L0
EXTERNAL PORT
3
8
ADDR
32
CNTRL
6
M0 DATA
M1 ADDR
M1 DATA
M2 ADDR
M2 DATA
MEMORY
M2
64K × 32
AD
MEMORY
M1
64K × 32
AD
MEMORY
M0
64K × 32
AD
INTEGER
KALU
INTEGER
JALU
32
DATA ADDRESS GENERATION
IAB
PC BTB IRQ
ADDR
FETCH
PROGRAM SEQUENCER
Y
REGISTER
FILE
32 × 32
MULTIPLIER
ALU
SHIFTER
DAB
128 128
X
REGISTER
FILE
32 × 32
MULTIPLIER
ALU
SHIFTER
DAB
128 128
I/O ADDRESS
INTERNAL MEMORY
COMPUTATIONAL BLOCKS
I/O PROCESSOR
LINK PORT
CONTROLLER
CONTROL/
STATUS/
BUFFERS
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
256
32 256
DMA DATA
LINK DATA
DMA ADDRESS
32
128
32
128
32
128
32
32
32 × 32 32 × 32
M0 ADDR