Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 98 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
JTAG Test And Emulation Port Timing
Table 67 and Figure 53 describe JTAG port operations.
Table 67. JTAG Port Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
TCK
JTG_TCK Period 20 20 ns
t
STAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High 4 4 ns
t
HTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High 4 4 ns
t
SSYS
System Inputs Setup Before JTG_TCK High
1
12 12 ns
t
HSYS
System Inputs Hold After JTG_TCK High
1
5 5 ns
t
TRSTW
JTG_TRST Pulse Width (measured in JTG_TCK cycles)
2
44TCK
Switching Characteristics
t
DTDO
JTG_TDO Delay from JTG_TCK Low 18 13.5 ns
t
DSYS
System Outputs Delay After JTG_TCK Low
3
22 17 ns
1
System Inputs = DMC0_DQ00–15, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_15–0, PG_15–0,
SMC0_ARDY_NORWT, SMC0_BR, SMC0_D15–0, SYS_BMODE0–2, SYS_HWRST, SYS_FAULT, SYS_FAULT, SYS_NMI_RESOUT, SYS_PWRGD, TWI0_SCL, TWI0_
SDA, TWI1_SCL, TWI1_SDA.
2
50 MHz Maximum.
3
System Outputs = DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ00–15, DMC0_LDM, DMC0_LDQS,
DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, JTG_EMU, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_
15–0, PG_15–0, SMC0_AMS0, SMC0_AOE_NORDV, SMC0_ARE, SMC0_AWE, SMC0_A01, SMC0_A02, SMC0_D15–0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT,
SYS_NMI_RESOUT, TWI0_SCL, TWI0_SDA, TWI1_SCL, TWI1_SDA.
Figure 53. JTAG Port Timing
JTG_TCK
JTG_TMS
JTG_TDI
JTG_TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS