Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 96 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
10/100 Ethernet MAC Controller Timing
Table 64 through Table 66 and Figure 50 through Figure 52
describe the 10/100 Ethernet MAC Controller operations.
Table 64. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter
1
V
DD_EXT
1.8 V/3.3 V Nominal
Min Max Unit
Timing Requirements
t
REFCLKF
ETHx_REFCLK Frequency (f
SCLK0
= SCLK0 Frequency) None 50 + 1% MHz
t
REFCLKW
ETHx_REFCLK Width (t
REFCLK
= ETHx_REFCLK Period) t
REFCLK
× 35% t
REFCLK
× 65% ns
t
REFCLKIS
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup) 4 ns
t
REFCLKIH
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold) 2.2 ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Figure 50. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 65. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter
1
V
DD_EXT
1.8 V/3.3 V Nominal
Min Max Unit
Switching Characteristics
t
REFCLKOV
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid) 14 ns
t
REFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold) 2 ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
Figure 51. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
t
REFCLKIS
t
REFCLKIH
ETHx_RXD1–0
ETHx_CRS
ETHx_RXERR
RMII_REF_CLK
t
REFCLKW
t
REFCLK
t
REFCLKOV
t
REFCLKOH
RMII_REF_CLK
ETHx_TXD1–0
ETHx_TXEN
t
REFCLK