Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 95 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
RSI Controller Timing
Table 63 and Figure 49 describe RSI controller timing.
Table 63. RSI Controller Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
ISU
Input Setup Time 11 9.6 ns
t
IH
Input Hold Time 2 2 ns
Switching Characteristics
f
PP
Clock Frequency Data Transfer Mode
1
41.67 41.67 MHz
t
WL
Clock Low Time 8 8 ns
t
WH
Clock High Time 8 8 ns
t
TLH
Clock Rise Time 3 3 ns
t
THL
Clock Fall Time 3 3 ns
t
ODLY
Output Delay Time During Data Transfer Mode 2.5 2.5 ns
t
OH
Output Hold Time –1 –1 ns
1
t
PP
= 1/f
PP
Figure 49. RSI Controller Timing
RSI_CLK
INPUT
OUTPUT
t
ISU
NOTES:
1 INPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
2 OUTPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
t
THL
t
TLH
t
WL
t
WH
t
PP
t
IH
t
ODLY
t
OH
V
OH (MIN)
V
OL (MAX)