Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 93 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADC Controller Module (ACM) Timing
Table 61 and Figure 48 describe ACM operations.
Note that the ACM clock (ACMx_CLK) frequency in MHz is
set by the following equation where CKDIV is a field in the
ACM_TC0 register and ranges from 1 to 255. Setup cycles (SC)
in Table 61 is also a field in the ACM_TC0 register and ranges
from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1
register that ranges from 0 to 15.
f
ACLK
f
SCLK1
CKDIV 1+
---------------------------=
t
ACLK
1
f
ACLK
-----------------=
Table 61. ACM Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SDR
SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK 3 ns
t
HDR
SPORT DRxPRI/DRxSEC Hold After ACMx_CLK 1.5 ns
Switching Characteristics
t
SCTLCS
ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS (SC + 1) × t
SCLK1
– 3 ns
t
HCTLCS
ACM Control (ACMx_A[4:0]) Hold After De-assertion of CS HC × t
ACLK
+ 0.1 ns
t
ACLKW
ACM Clock Pulse Width (t
SCLK1
/2) × (CLKDIV + 1) – 1.5 ns
t
ACLK
ACM Clock Period
1
[t
SCLK1
× (CKDIV + 1)] or [16] ns
t
HCSACLK
CS Hold to ACMx_CLK Edge –0.1 ns
t
SCSACLK
CS Setup to ACMx_CLK Edge t
ACLK
– 3.5 ns
1
Whichever is greater.
Figure 48. ACM Timing
CS
CSPOL = 1/0
t
SCSACLK
ACM
CONTROLS
DRxPRI/
DRxSEC
t
ACLK
t
SCTLCS
t
SDR
t
HDR
ACM_CLK
CLKPOL = 1/0
t
HCSACLK
t
HCTLCS