Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 92 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Up/Down Counter/Rotary Encoder Timing
Pulse Width Modulator (PWM) Timing
Table 60 and Figure 47 describe PWM operations.
Table 59. Up/Down Counter/Rotary Encoder Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width 2 × t
SCLK0
2 × t
SCLK0
ns
Figure 46. Up/Down Counter/Rotary Encoder Timing
CNT_UD
CNT_DG
CNT_ZM
t
WCOUNT
Table 60. PWM Timing
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirement
t
ES
External Sync Pulse Width 2 × t
SCLK0
ns
Switching Characteristics
t
DODIS
Output Inactive (OFF) After Trip Input
1
15 ns
t
DOE
Output Delay After External Sync
1,
2
2 × t
SCLK0
+ 5.5 5 × t
SCLK0
+ 14 ns
1
PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
2
When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock. For more information, see the ADSP-BF60x Blackfin Processor Hardware Reference.
Figure 47. PWM Timing
PWM_TRIP
PWM_SYNC
(AS INPUT)
t
ES
t
DOE
OUTPUT
t
DODIS