Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 91 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
General-Purpose Port Timing
Table 57 and Figure 44 describe general-purpose
port operations.
Timer Cycle Timing
Table 58 and Figure 45 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK0
/4) MHz. The Period Value value is the timer
period assigned in the TMx_TMRn_PER register and can range
from 2 to 2
32
– 1.
Table 57. General-Purpose Port Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirement
t
WFI
General-Purpose Port Pin Input Pulse Width 2 × t
SCLK0
ns
Figure 44. General-Purpose Port Timing
GPIO INPUT
t
WFI
Table 58. Timer Cycle Timing
Parameter
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
WL
Timer Pulse Width Input Low (Measured In
SCLK0 Cycles)
1
2 × t
SCLK0
2 × t
SCLK0
ns
t
WH
Timer Pulse Width Input High (Measured In
SCLK0 Cycles)
1
2 × t
SCLK0
2 × t
SCLK0
ns
Switching Characteristics
t
HTO
Timer Pulse Width Output (Measured In
SCLK0 Cycles)
t
SCLK0
× Period
Value
t
SCLK0
× Period
Value
t
SCLK0
× Period
Value
t
SCLK0
× Period
Value
ns
1
The minimum pulse widths apply for TMx signals in width capture and external clock modes.
Figure 45. Timer Cycle Timing
TMR OUTPUT
TMR INPUT
t
WH
, t
WL
t
HTO