Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 89 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
Table 56. SPI Port—SPI_RDY Timing
V
DD_EXT
1.8 V/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SRDYSCKM0
Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 0
(2.5 + 1.5 × BAUD
1
) × t
SCLK1
+
17.5
ns
t
SRDYSCKM1
Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 1
(1.5 × BAUD
1
) × t
SCLK1
+ 17.5 ns
Switching Characteristic
t
SRDYSCKM
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0
(STOP, LEAD, LAG = 0)
3 × t
SCLK1
4 × t
SCLK1
+ 17.5 ns
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1
(STOP, LEAD, LAG = 0)
(4 + 1.5 × BAUD
1
) × t
SCLK1
(5 + 1.5 × BAUD
1
) × t
SCLK1
+
17.5
ns
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEAD,
LAG = 0)
(3 + 0.5 × BAUD
1
) × t
SCLK1
(4 + 0.5 × BAUD
1
) × t
SCLK1
+
17.5
ns
1
BAUD value set using the SPI_CLK.BAUD bits.
Figure 41. SPI_RDY Setup Before SPI_CLK with CPHA = 0
Figure 42. SPI_RDY Setup Before SPI_CLK with CPHA = 1
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM0
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
t
SRDYSCKM1
SPI_RDY