Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 85 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 52 and Figure 36 describe SPI port slave operations. Note
that:
• In dual mode data transmit the SPI_MOSI signal is also an
output.
• In quad mode data transmit the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also outputs.
• In dual mode data receive the SPI_MISO signal is also an
input.
• In quad mode data receive the SPI_MISO, SPI_D2, and
SPI_D3 signals are also inputs.
Table 52. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
V
DD_EXT
1.8 V/3.3 V Nominal
Min Max Unit
Timing Requirements
t
SPICHS
SPI_CLK High Period for Data Transmit
1
[0.5 × t
SCLK1
– 1.5] or [7.0] ns
SPI_CLK High Period for Data Receive
1
[0.5 × t
SCLK1
– 1.5] or [4.5] ns
t
SPICLS
SPI_CLK Low Period for Data Transmit
1
[0.5 × t
SCLK1
– 1.5] or [7.0] ns
SPI_CLK Low Period for Data Receive
1
[0.5 × t
SCLK1
– 1.5] or [4.5] ns
t
SPICLK
SPI_CLK Period for Data Transmit
1
[t
SCLK1
– 1.5] or [17] ns
SPI_CLK Period for Data Receive
1
[t
SCLK1
– 1.5] or [12] ns
t
HDS
Last SPI_CLK Edge to SPI_SS Not Asserted 5 ns
t
SPITDS
Sequential Transfer Delay 0.5 × t
SPICLK
– 1.5 ns
t
SDSCI
SPI_SS Assertion to First SPI_CLK Edge 10.5 ns
t
SSPID
Data Input Valid to SPI_CLK Edge (Data Input Setup) 2.0 ns
t
HSPID
SPI_CLK Sampling Edge to Data Input Invalid 1.6 ns
Switching Characteristics
t
DSOE
SPI_SS Assertion to Data Out Active 0 14 ns
t
DSDHI
SPI_SS Deassertion to Data High Impedance 0 12.5 ns
t
DDSPID
SPI_CLK Edge to Data Out Valid (Data Out Delay) 14 ns
t
HDSPID
SPI_CLK Edge to Data Out Invalid (Data Out Hold) 0 ns
1
Whichever is greater.