Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 81 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
The SPT_TDV output signal becomes active in SPORT multi-
channel mode. During transmit slots (enabled with active
channel selection registers) the SPT_TDV is asserted for com-
munication with external devices.
Table 49. Serial Ports—TDV (Transmit Data Valid)
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Switching Characteristics
t
DRDVEN
Data-Valid Enable Delay from Drive Edge of External Clock
1
22ns
t
DFDVEN
Data-Valid Disable Delay from Drive Edge of External Clock
1
18.8 14 ns
t
DRDVIN
Data-Valid Enable Delay from Drive Edge of Internal Clock
1
–1 –1 ns
t
DFDVIN
Data-Valid Disable Delay from Drive Edge of Internal Clock
1
3.5 3.5 ns
1
Referenced to drive edge.
Figure 33. Serial Ports—Transmit Data Valid Internal and External Clock
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
t
DRDVEN
t
DFDVEN
DRIVE EDGE DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
t
DRDVIN
t
DFDVIN
SPT_A/BTDV
SPT_A/BTDV