Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 78 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 47. Serial Ports—Internal Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)
1
16.8 12
ns
t
HFSI
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)
1
0–0.5
ns
t
SDRI
Receive Data Setup Before SPT_CLK
1
4.8 3.4 ns
t
HDRI
Receive Data Hold After SPT_CLK
1
1.5 1.5 ns
Switching Characteristics
t
DFSI
Frame Sync Delay After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)
2
3.5 3.5 ns
t
HOFSI
Frame Sync Hold After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)
2
–1.0 –1.0 ns
t
DDTI
Transmit Data Delay After SPT_CLK
2
3.5 3.5 ns
t
HDTI
Transmit Data Hold After SPT_CLK
2
–1.25 –1.25 ns
t
SCLKIW
SPT_CLK Width for Internal SPT_CLK
Data/FS Transmit
3
[0.5 × t
SCLK1
– 1.5] or [4.5] [0.5 × t
SCLK1
– 1.5] or [4.5] ns
SPT_CLK Width for Internal SPT_CLK
Data/FS Receive
[0.5 × t
SCLK1
– 1.5] or [6.5] [0.5 × t
SCLK1
– 1.5] or [6.5] ns
t
SPTCLK
SPT_CLK Period for Internal SPT_CLK
Data/FS Transmit
3
[t
SCLK1
– 1.5] or [12] [t
SCLK1
– 1.5] or [12] ns
t
SPTCLK
SPT_CLK Period for Internal SPT_CLK
Data/FS Receive
3
[t
SCLK1
– 1.5] or [16] [t
SCLK1
– 1.5] or [16] ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Whichever is greater.