Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 77 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SPT_CLK) width. In Figure 31 either the rising edge or the fall-
ing edge of SPT_CLK (external or internal) can be used as the
active sampling edge.
Table 46. Serial Ports—External Clock
V
DD_EXT
1.8 V Nominal
V
DD_EXT
3.3 V Nominal
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)
1
22 ns
t
HFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)
1
2.7 2.7 ns
t
SDRE
Receive Data Setup Before Receive SPT_CLK
1
22 ns
t
HDRE
Receive Data Hold After SPT_CLK
1
2.7 2.7 ns
t
SCLKW
SPT_CLK Width for External SPT_CLK Data/FS
Receive
2
[0.5 × t
SCLK1
– 0.5] or [5.5] [0.5 × t
SCLK1
– 0.5] or [5.5] ns
SPT_CLK Width for External SPT_CLK Data/FS
Transmit
2
[0.5 × t
SCLK1
– 0.5] or [8] [0.5 × t
SCLK1
– 0.5] or [8] ns
t
SPTCLK
SPT_CLK Period for External SPT_CLK Data/FS
Receive
2
[t
SCLK1
– 1] or [12] [t
SCLK1
– 1] or [12] ns
SPT_CLK Period for External SPT_CLK Data/FS
Transmit
2
[t
SCLK1
– 1] or [17] [t
SCLK1
– 1] or [17] ns
Switching Characteristics
t
DFSE
Frame Sync Delay After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)
3
19.3 14.5 ns
t
HOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)
3
22 ns
t
DDTE
Transmit Data Delay After Transmit SPT_CLK
3
18.8 14 ns
t
HDTE
Transmit Data Hold After Transmit SPT_CLK
3
22 ns
1
Referenced to sample edge.
2
Whichever is greater.
3
Referenced to drive edge.