Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 76 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 45. Link Ports—Transmit
V
DD_EXT
1.8 V Nominal/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SLACH
LP_ACK Setup Before LP_CLK Low 2 × t
SCLK0
+ 10 ns
t
HLACH
LP_ACK Hold After LP_CLK Low 0 ns
Switching Characteristics
t
DLDCH
Data Delay After LP_CLK High 2.5 ns
t
HLDCH
Data Hold After LP_CLK High –1 ns
t
LCLKTWL
LP_CLK Width Low 0.4 × t
LCLK
0.6 × t
LCLK
ns
t
LCLKTWH
LP_CLK Width High 0.4 × t
LCLK
0.6 × t
LCLK
ns
t
DLACLK
LP_CLK Low Delay After LP_ACK High t
SCLK0
+ 4 (2 × t
SCLK0
) + t
LCLK
+ 10 ns
Figure 30. Link Ports—Transmit
LP_CLK
LP_Dx
(DATA)
LP_ACK (IN)
OUT
t
DLDCH
t
HLDCH
t
SLACH
t
HLACH
t
DLACLK
t
LCLKTWH
t
LCLKTWL
LAST BYTE
TRANSMITTED
FIRST BYTE
TRANSMITTED
1
NOTES
The t
SLACH
and t
HLACH
specifications apply only to the LP_ACK falling edge. If these specifications are met,
LP_CLK would extend and the dotted LP_CLK falling edge would not occur as shown. The position of the
dotted falling edge can be calculated using the t
LCLKTWH
specification. t
LCLKTWH
Min should be used for t
SLACH
and t
LCLKTWH
Max for t
HLACH
.