Datasheet
Table Of Contents
- Blackfin Dual Core Embedded Processor
- Features
- Memory
- Table Of Contents
- Revision History
- General Description
- ADSP-BF60x Detailed Signal Descriptions
- 349-Ball CSP_BGA Signal Descriptions
- GP I/O Multiplexing for 349-Ball CSP_BGA
- ADSP-BF60x Designer Quick Reference
- Specifications
- Operating Conditions
- Electrical Characteristics
- Processor — Absolute Maximum Ratings
- ESD Sensitivity
- Processor — Package Information
- Timing Specifications
- Clock and Reset Timing
- Power-Up Reset Timing
- Asynchronous Read
- Asynchronous Flash Read
- Asynchronous Page Mode Read
- Synchronous Burst Flash Read
- Asynchronous Write
- Asynchronous Flash Write
- All Accesses
- Bus Request/Bus Grant
- DDR2 SDRAM Clock and Control Cycle Timing
- DDR2 SDRAM Read Cycle Timing
- DDR2 SDRAM Write Cycle Timing
- Mobile DDR SDRAM Clock and Control Cycle Timing
- Mobile DDR SDRAM Read Cycle Timing
- Mobile DDR SDRAM Write Cycle Timing
- Enhanced Parallel Peripheral Interface Timing
- Link Ports
- Serial Ports
- Serial Peripheral Interface (SPI) Port—Master Timing
- Serial Peripheral Interface (SPI) Port—Slave Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing
- Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing
- Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
- General-Purpose Port Timing
- Timer Cycle Timing
- Up/Down Counter/Rotary Encoder Timing
- Pulse Width Modulator (PWM) Timing
- ADC Controller Module (ACM) Timing
- Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
- CAN Interface
- Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
- RSI Controller Timing
- 10/100 Ethernet MAC Controller Timing
- JTAG Test And Emulation Port Timing
- Output Drive Currents
- Environmental Conditions
- ADSP-BF60x 349-Ball CSP_BGA Ball Assignments
- Outline Dimensions
- Automotive Products
- Ordering Guide
Rev. 0 | Page 75 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path length differ-
ence between LP_Dx (data) and LP_CLK. Setup skew is the
maximum delay that can be introduced in LP_Dx relative to
LP_CLK:
(setup skew = t
LCLKTWH
min – t
DLDCH
– t
SLDCL
). Hold skew is the
maximum delay that can be introduced in LP_CLK relative to
LP_Dx: (hold skew = t
LCLKTWL
min – t
HLDCH
– t
HLDCL
).
Table 44. Link Ports—Receive
V
DD_EXT
1.8 V Nominal/3.3 V Nominal
Parameter Min Max Unit
Timing Requirements
t
SLDCL
Data Setup Before LP_CLK Low 2 ns
t
HLDCL
Data Hold After LP_CLK Low 3 ns
t
LCLKIW
LP_CLK Period
1
[t
SCLK0
– 1] or [12] ns
t
LCLKRWL
LP_CLK Width Low
1
[0.5 × t
SCLK0
– 0.5] or [5.5] ns
t
LCLKRWH
LP_CLK Width High
1
[0.5 × t
SCLK0
– 0.5] or [5.5] ns
Switching Characteristic
t
DLALC
LP_ACK Low Delay After LP_CLK Low
2
1.5 × t
SCLK0
+ 4 2.5 × t
SCLK0
+ 12 ns
1
Whichever is greater.
2
LP_ACK goes low with t
DLALC
relative to rise of LP_CLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
Figure 29. Link Ports—Receive
LP_D7–0
LP_CLK
LP_ACK (OUT)
t
HLDCL
t
SLDCL
IN
t
LCLKRWH
t
LCLKRWL
t
LCLKIW
t
DLALC